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Commit 24ff30a8 authored by Phani Kumar Uppalapati's avatar Phani Kumar Uppalapati
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ASoC: wcd934x: Update master clock sequence for wcd934x codec 



Update master clock sequence for wcd934x codec to avoid mute
when codec core goes in and comes out of power collapse.

Change-Id: Id85c8437bf99d1b0bd1ab8f7e8a7f3fcf7e93856
Signed-off-by: default avatarPhani Kumar Uppalapati <phaniu@codeaurora.org>
parent ea4719da

sound/soc/codecs/wcd934x/wcd934x.c

+1 −1
Original line number Diff line number Diff line
@@ -7859,9 +7859,9 @@ static int tavil_dig_core_remove_power_collapse(struct snd_soc_codec *codec) 


	snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);

	snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);

	snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);

	snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x00);

	snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x02);

	snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);



	wcd9xxx_set_power_state(tavil->wcd9xxx,

			WCD_REGION_POWER_COLLAPSE_REMOVE,

sound/soc/codecs/wcd9xxx-resmgr-v2.c

+8 −5
Original line number Diff line number Diff line
@@ -247,15 +247,15 @@ static int wcd_resmgr_enable_clk_mclk(struct wcd9xxx_resmgr_v2 *resmgr) 
			 * to CLK_SYS_MCLK_PRG

			 */

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_MCLK_PRG, 0x91, 0x91);

					WCD934X_CLK_SYS_MCLK_PRG, 0x80, 0x80);

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_MCLK_PRG, 0x30, 0x10);

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00);

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_INT_CLK_TEST2, 0x04,

					0x04);

					WCD934X_CLK_SYS_MCLK_PRG, 0x01, 0x01);

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_INT_CLK_TEST2, 0x04,

					0x00);

					WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00);

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD93XX_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,

					0x01, 0x01);
@@ -311,6 +311,9 @@ static int wcd_resmgr_disable_clk_mclk(struct wcd9xxx_resmgr_v2 *resmgr) 
					0x08, 0x08);

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x02);

			/* Disable clock buffer */

			wcd_resmgr_codec_reg_update_bits(resmgr,

					WCD934X_CLK_SYS_MCLK_PRG, 0x80, 0x00);

			resmgr->clk_type = WCD_CLK_RCO;

		} else {

			wcd_resmgr_codec_reg_update_bits(resmgr,