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Commit 23ed5efc authored by Vikash Garodia's avatar Vikash Garodia
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ARM: dts: msm: Fix DCVS load for SDM660



DCVS table specifies the low and high load interms
of mbs per sec. Clock frequency is derived from
this load alongwith cycles required per mb. For
starlord, the DCVS low load was incorrect which
made the decoder session to run in SVS instead
of SVS+. The change now fix it to proper load.

Change-Id: I46dd772aa349b94a75472477e24cabe80c088165
CRs-Fixed: 2007776
Signed-off-by: default avatarVikash Garodia <vgarodia@codeaurora.org>
parent 2aa89ab3
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+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@

		qcom,dcvs-tbl =
			/* Dec UHD@30 All decoder - NOM to SVS+ */
			<897600 734400 979200 0x3f00000c>,
			<897600 783360 979200 0x3f00000c>,

			/* Dec DCI@24 HEVC - NOM to SVS+ */
			<816000 734400 829440 0x0c000000>,