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Commit 23958fda authored by Odelu Kukatla's avatar Odelu Kukatla
Browse files

clk: qcom: Remove few multimedia clocks for sdm630 



Some of the multimedia subsystem clocks are not present in sdm630,
so remove them from registering with clock framework.

Change-Id: I073dc25fa0a0665a5b9b10c4ea977767a1e286d1
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 3ba1a36a

Documentation/devicetree/bindings/clock/qcom,mmcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties : 
			"qcom,mmcc-msm8974"

			"qcom,mmcc-msm8996"

			"qcom,mmcc-sdm660"

			"qcom,mmcc-sdm630"



- reg : shall contain base register location and length

- #clock-cells : shall contain 1

arch/arm/boot/dts/qcom/sdm630.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -953,7 +953,7 @@ 
	};



	clock_mmss: clock-controller@c8c0000 {

		compatible = "qcom,mmcc-sdm660";

		compatible = "qcom,mmcc-sdm630";

		reg = <0xc8c0000 0x40000>;

		vdd_mx_mmss-supply = <&pm660l_s5_level>;

		vdd_dig_mmss-supply = <&pm660l_s3_level>;

drivers/clk/qcom/mmcc-sdm660.c

+16 −0
Original line number Diff line number Diff line
@@ -3002,6 +3002,7 @@ static const struct qcom_cc_desc mmcc_660_desc = { 


static const struct of_device_id mmcc_660_match_table[] = {

	{ .compatible = "qcom,mmcc-sdm660" },

	{ .compatible = "qcom,mmcc-sdm630" },

	{ }

};

MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
@@ -3010,11 +3011,15 @@ static int mmcc_660_probe(struct platform_device *pdev) 
{

	int ret = 0;

	struct regmap *regmap;

	bool is_sdm630 = 0;



	regmap = qcom_cc_map(pdev, &mmcc_660_desc);

	if (IS_ERR(regmap))

		return PTR_ERR(regmap);



	is_sdm630 = of_device_is_compatible(pdev->dev.of_node,

						"qcom,mmcc-sdm630");



	/* PLLs connected on Mx rails of MMSS_CC  */

	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_mmss");

	if (IS_ERR(vdd_mx.regulator[0])) {
@@ -3048,6 +3053,17 @@ static int mmcc_660_probe(struct platform_device *pdev) 
	clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config);

	clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config);



	if (is_sdm630) {

		mmcc_660_desc.clks[BYTE1_CLK_SRC] = 0;

		mmcc_660_desc.clks[MMSS_MDSS_BYTE1_CLK] = 0;

		mmcc_660_desc.clks[MMSS_MDSS_BYTE1_INTF_DIV_CLK] = 0;

		mmcc_660_desc.clks[MMSS_MDSS_BYTE1_INTF_CLK] = 0;

		mmcc_660_desc.clks[ESC1_CLK_SRC] = 0;

		mmcc_660_desc.clks[MMSS_MDSS_ESC1_CLK] = 0;

		mmcc_660_desc.clks[PCLK1_CLK_SRC] = 0;

		mmcc_660_desc.clks[MMSS_MDSS_PCLK1_CLK] = 0;

	}



	ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register MMSS clocks\n");