Merge "clk: qcom: Remove non-op BRANCH_HALT_NO_CHECK_ON_DISABLE flag" (22d4148b) · Commits · e / devices / android_kernel_sony_msm8998

drivers/clk/qcom/clk-branch.c

+0 −3

Original line number	Original line	Diff line number	Diff line
	@@ -83,9 +83,6 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,

	if (br->halt_check == BRANCH_HALT_DELAY \|\| (!enabling && voted)) {		if (br->halt_check == BRANCH_HALT_DELAY \|\| (!enabling && voted)) {
	udelay(10);		udelay(10);
	} else if ((br->halt_check == BRANCH_HALT_NO_CHECK_ON_DISABLE) &&
	!enabling) {
	return 0;
	} else if (br->halt_check == BRANCH_HALT_ENABLE \|\|		} else if (br->halt_check == BRANCH_HALT_ENABLE \|\|
	br->halt_check == BRANCH_HALT \|\|		br->halt_check == BRANCH_HALT \|\|
	(enabling && voted)) {		(enabling && voted)) {

drivers/clk/qcom/clk-branch.h

+0 −4

Original line number	Original line	Diff line number	Diff line
	@@ -42,10 +42,6 @@ struct clk_branch {
	#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */		#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
	#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE \| BRANCH_VOTED)		#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE \| BRANCH_VOTED)
	#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */		#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
	/* No halt check during clk disable for the clocks controlled by other masters
	* via voting registers like SMMU clocks.
	*/
	#define BRANCH_HALT_NO_CHECK_ON_DISABLE 4

	struct clk_regmap clkr;		struct clk_regmap clkr;
	};		};

drivers/clk/qcom/gcc-msm8996.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -1253,7 +1253,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {

	static struct clk_branch gcc_mmss_bimc_gfx_clk = {		static struct clk_branch gcc_mmss_bimc_gfx_clk = {
	.halt_reg = 0x9010,		.halt_reg = 0x9010,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x9010,		.enable_reg = 0x9010,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2692,7 +2692,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {

	static struct clk_branch gcc_smmu_aggre0_axi_clk = {		static struct clk_branch gcc_smmu_aggre0_axi_clk = {
	.halt_reg = 0x81014,		.halt_reg = 0x81014,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x81014,		.enable_reg = 0x81014,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2717,7 +2717,7 @@ static struct clk_gate2 gcc_aggre0_noc_qosgen_extref_clk = {

	static struct clk_branch gcc_smmu_aggre0_ahb_clk = {		static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
	.halt_reg = 0x81018,		.halt_reg = 0x81018,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x81018,		.enable_reg = 0x81018,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2871,7 +2871,7 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {

	static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {		static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {
	.halt_reg = 0x7d010,		.halt_reg = 0x7d010,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x7d010,		.enable_reg = 0x7d010,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2884,7 +2884,7 @@ static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {

	static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {		static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
	.halt_reg = 0x7d014,		.halt_reg = 0x7d014,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x7d014,		.enable_reg = 0x7d014,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),

drivers/clk/qcom/gcc-msmfalcon.c

+6 −6

Original line number	Original line	Diff line number	Diff line
	@@ -1173,7 +1173,7 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {

	static struct clk_branch gcc_bimc_gfx_clk = {		static struct clk_branch gcc_bimc_gfx_clk = {
	.halt_reg = 0x7106c,		.halt_reg = 0x7106c,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x7106c,		.enable_reg = 0x7106c,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -1711,7 +1711,7 @@ static struct clk_branch gcc_gp3_clk = {

	static struct clk_branch gcc_gpu_bimc_gfx_clk = {		static struct clk_branch gcc_gpu_bimc_gfx_clk = {
	.halt_reg = 0x71010,		.halt_reg = 0x71010,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x71010,		.enable_reg = 0x71010,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -1737,7 +1737,7 @@ static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {

	static struct clk_branch gcc_gpu_cfg_ahb_clk = {		static struct clk_branch gcc_gpu_cfg_ahb_clk = {
	.halt_reg = 0x71004,		.halt_reg = 0x71004,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x71004,		.enable_reg = 0x71004,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2516,7 +2516,7 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {

	static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {		static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
	.halt_reg = 0x7d014,		.halt_reg = 0x7d014,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x7d014,		.enable_reg = 0x7d014,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2529,7 +2529,7 @@ static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {

	static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {		static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {
	.halt_reg = 0x7d048,		.halt_reg = 0x7d048,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x7d048,		.enable_reg = 0x7d048,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),
	@@ -2542,7 +2542,7 @@ static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {

	static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = {		static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = {
	.halt_reg = 0x7e048,		.halt_reg = 0x7e048,
	.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE,		.halt_check = BRANCH_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x7e048,		.enable_reg = 0x7e048,
	.enable_mask = BIT(0),		.enable_mask = BIT(0),