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Commit 205f9328 authored by Dave Jones's avatar Dave Jones Committed by Ingo Molnar
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x86: add new cache descriptor 



The latest rev of Intel doc AP-485 details a new cache
descriptor that we don't yet support.
A 6MB 24-way assoc L2 cache.

Signed-off-by: default avatarDave Jones <davej@redhat.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 492c2e47

arch/x86/kernel/cpu/intel_cacheinfo.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -62,6 +62,7 @@ static struct _cache_table cache_table[] __cpuinitdata = 
	{ 0x4b, LVL_3,      8192 },	/* 16-way set assoc, 64 byte line size */

	{ 0x4b, LVL_3,      8192 },	/* 16-way set assoc, 64 byte line size */

	{ 0x4c, LVL_3,     12288 },	/* 12-way set assoc, 64 byte line size */

	{ 0x4c, LVL_3,     12288 },	/* 12-way set assoc, 64 byte line size */

	{ 0x4d, LVL_3,     16384 },	/* 16-way set assoc, 64 byte line size */

	{ 0x4d, LVL_3,     16384 },	/* 16-way set assoc, 64 byte line size */

	{ 0x4e, LVL_2,      6144 },	/* 24-way set assoc, 64 byte line size */

	{ 0x60, LVL_1_DATA, 16 },	/* 8-way set assoc, sectored cache, 64 byte line size */

	{ 0x60, LVL_1_DATA, 16 },	/* 8-way set assoc, sectored cache, 64 byte line size */

	{ 0x66, LVL_1_DATA, 8 },	/* 4-way set assoc, sectored cache, 64 byte line size */

	{ 0x66, LVL_1_DATA, 8 },	/* 4-way set assoc, sectored cache, 64 byte line size */

	{ 0x67, LVL_1_DATA, 16 },	/* 4-way set assoc, sectored cache, 64 byte line size */

	{ 0x67, LVL_1_DATA, 16 },	/* 4-way set assoc, sectored cache, 64 byte line size */