Commit 1f3a2c6e authored Jan 30, 2015 by James Hogan Committed by Ralf Baechle Mar 27, 2015

MIPS: MSA: Fix big-endian FPR_IDX implementation



The maximum word size is 64-bits since MSA state is saved using st.d
which stores two 64-bit words, therefore reimplement FPR_IDX using xor,
and only within each 64-bit word.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9169/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 466aec5f

arch/mips/include/asm/processor.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -105,7 +105,7 @@ union fpureg {
		#ifdef CONFIG_CPU_LITTLE_ENDIAN
		# define FPR_IDX(width, idx) (idx)
		#else
		# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx))
		# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
		#endif

		#define BUILD_FPR_ACCESS(width) \