Commit 1ef48593 authored Jul 16, 2011 by Will Simoneau Committed by David S. Miller Jul 16, 2011

sparc: sun4m SMP: fix wrong shift instruction in IPI handler



This shift instruction appears to be shifting in the wrong direction.
Without this change, my SparcStation-20MP hangs just after bringing up
the second CPU:

Entering SMP Mode...
Starting CPU 2 at f02b4e90
Brought up 2 CPUs
Total of 2 processors activated (99.52 BogoMIPS).
   *** stuck ***

Signed-off-by: Will Simoneau <simoneau@ele.uri.edu>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 6d999da4

arch/sparc/kernel/entry.S

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -293,7 +293,7 @@ maybe_smp4m_msg:
	WRITE_PAUSE		WRITE_PAUSE
	wr %l4, PSR_ET, %psr		wr %l4, PSR_ET, %psr
	WRITE_PAUSE		WRITE_PAUSE
	sll %o3, 28, %o2 ! shift for simpler checks below		srl %o3, 28, %o2 ! shift for simpler checks below
	maybe_smp4m_msg_check_single:		maybe_smp4m_msg_check_single:
	andcc %o2, 0x1, %g0		andcc %o2, 0x1, %g0
	beq,a maybe_smp4m_msg_check_mask		beq,a maybe_smp4m_msg_check_mask