ASoC: wcd934x: Adjust DMIC clock based on sample rate

Currently DMIC clock is set at 4.8MHz for all sampling rates.
For optimal power, sampling rates <=48KHz and dmic clock <=2.4MHz,
it should be set to the value read from device tree and others
should be set to 2.4MHz.

Change-Id: If68fea97d2f0b27432e61d73d6841a2b194bb63b
Signed-off-by: Meng Wang <mwang@codeaurora.org>