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Commit 1bd558b8 authored by Ben Hutchings's avatar Ben Hutchings Committed by Greg Kroah-Hartman
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x86: cpufeatures: Sort feature word 7 



This will make it clearer which bits are allocated, in case we need to
assign more feature bits for later backports.

Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 68522ac3

arch/x86/include/asm/cpufeatures.h

+2 −4
Original line number Diff line number Diff line
@@ -196,13 +196,10 @@ 
#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */



#define X86_FEATURE_INTEL_PT	( 7*32+15) /* Intel Processor Trace */

#define X86_FEATURE_RSB_CTXSW	( 7*32+19) /* "" Fill RSB on context switches */



#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */

#define X86_FEATURE_SSBD	( 7*32+17) /* Speculative Store Bypass Disable */



/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */

#define X86_FEATURE_KAISER	( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */

#define X86_FEATURE_RSB_CTXSW	( 7*32+19) /* "" Fill RSB on context switches */



#define X86_FEATURE_USE_IBPB	( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled*/

#define X86_FEATURE_USE_IBRS_FW	( 7*32+22) /* "" Use IBRS during runtime firmware calls */
@@ -215,6 +212,7 @@ 
#define X86_FEATURE_ZEN		( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */

#define X86_FEATURE_L1TF_PTEINV	( 7*32+29) /* "" L1TF workaround PTE inversion */

#define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */

#define X86_FEATURE_KAISER	( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */



/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */