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Commit 1b3c3b33 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm: set dma_mask properly"

parents ae428833 25f70927

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+6 −5
Original line number Diff line number Diff line
@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git 


The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10755 bytes, from 2015-09-14 20:46:55)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67771 bytes, from 2015-09-14 20:46:55)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63970 bytes, from 2015-09-14 20:50:12)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2015 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)



Permission is hereby granted, free of charge, to any person obtaining

a copy of this software and associated documentation files (the

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+428 −65

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/adreno/a4xx.xml.h

+1205 −62

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+92 −9
Original line number Diff line number Diff line
@@ -102,11 +102,17 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00020000);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);

	/* Early A430's have a timing issue with SP/TP power collapse;

	   disabling HW clock gating prevents it. */

	if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)

		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);

	else

		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0);

}





static void a4xx_me_init(struct msm_gpu *gpu)

{

	struct msm_ringbuffer *ring = gpu->rb;
@@ -141,7 +147,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	uint32_t *ptr, len;

	int i, ret;



	if (adreno_is_a4xx(adreno_gpu)) {

	if (adreno_is_a420(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);

		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);

		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
@@ -150,6 +156,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);

		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);

		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);

	} else if (adreno_is_a430(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);

		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);

		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);

		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);

		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);

		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);

	} else {

		BUG();

	}
@@ -161,6 +174,10 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10);

	gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);



	if (adreno_is_a430(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30);

	}



	 /* Enable the RBBM error reporting bits */

	gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);
@@ -183,6 +200,14 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	/* Turn on performance counters: */

	gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01);



	/* use the first CP counter for timestamp queries.. userspace may set

	 * this as well but it selects the same counter/countable:

	 */

	gpu_write(gpu, REG_A4XX_CP_PERFCTR_CP_SEL_0, CP_ALWAYS_COUNT);



	if (adreno_is_a430(adreno_gpu))

		gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07);



	/* Disable L2 bypass to avoid UCHE out of bounds errors */

	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000);

	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000);
@@ -190,6 +215,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) |

			(adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));



	/* On A430 enable SP regfile sleep for power savings */

	/* TODO downstream does this for !420, so maybe applies for 405 too? */

	if (!adreno_is_a420(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,

			0x00000441);

		gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,

			0x00000441);

	}



	a4xx_enable_hwcg(gpu);



	/*
@@ -204,10 +238,6 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val);

	}



	ret = adreno_hw_init(gpu);

	if (ret)

		return ret;



	/* setup access protection: */

	gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007);
@@ -263,6 +293,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0);



	a4xx_me_init(gpu);



	return 0;

}
@@ -512,12 +543,63 @@ static void a4xx_dump(struct msm_gpu *gpu) 
	adreno_dump(gpu);

}



static int a4xx_pm_resume(struct msm_gpu *gpu) {

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	int ret;



	ret = msm_gpu_pm_resume(gpu);

	if (ret)

		return ret;



	if (adreno_is_a430(adreno_gpu)) {

		unsigned int reg;

		/* Set the default register values; set SW_COLLAPSE to 0 */

		gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);

		do {

			udelay(5);

			reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS);

		} while (!(reg & A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON));

	}

	return 0;

}



static int a4xx_pm_suspend(struct msm_gpu *gpu) {

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	int ret;



	ret = msm_gpu_pm_suspend(gpu);

	if (ret)

		return ret;



	if (adreno_is_a430(adreno_gpu)) {

		/* Set the default register values; set SW_COLLAPSE to 1 */

		gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778001);

	}

	return 0;

}



static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)

{

	uint32_t hi, lo, tmp;



	tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI);

	do {

		hi = tmp;

		lo = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);

		tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI);

	} while (tmp != hi);



	*value = (((uint64_t)hi) << 32) | lo;



	return 0;

}



static const struct adreno_gpu_funcs funcs = {

	.base = {

		.get_param = adreno_get_param,

		.hw_init = a4xx_hw_init,

		.pm_suspend = msm_gpu_pm_suspend,

		.pm_resume = msm_gpu_pm_resume,

		.pm_suspend = a4xx_pm_suspend,

		.pm_resume = a4xx_pm_resume,

		.recover = a4xx_recover,

		.last_fence = adreno_last_fence,

		.submit = adreno_submit,
@@ -529,6 +611,7 @@ static const struct adreno_gpu_funcs funcs = { 
		.show = a4xx_show,

#endif

	},

	.get_timestamp = a4xx_get_timestamp,

};



struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)

drivers/gpu/drm/msm/adreno/adreno_common.xml.h

+24 −6
Original line number Diff line number Diff line
@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git 


The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10755 bytes, from 2015-09-14 20:46:55)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67771 bytes, from 2015-09-14 20:46:55)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63970 bytes, from 2015-09-14 20:50:12)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2015 by the following authors:

Copyright (C) 2013-2016 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)



Permission is hereby granted, free of charge, to any person obtaining

a copy of this software and associated documentation files (the
@@ -119,6 +120,23 @@ enum adreno_rb_copy_control_mode { 
	RB_COPY_DEPTH_STENCIL = 5,

};



enum a3xx_rop_code {

	ROP_CLEAR = 0,

	ROP_NOR = 1,

	ROP_AND_INVERTED = 2,

	ROP_COPY_INVERTED = 3,

	ROP_AND_REVERSE = 4,

	ROP_INVERT = 5,

	ROP_NAND = 7,

	ROP_AND = 8,

	ROP_EQUIV = 9,

	ROP_NOOP = 10,

	ROP_OR_INVERTED = 11,

	ROP_OR_REVERSE = 13,

	ROP_OR = 14,

	ROP_SET = 15,

};



enum a3xx_render_mode {

	RB_RENDERING_PASS = 0,

	RB_TILING_PASS = 1,