Merge "arm64: cache: change ARCH_DMA_MINALIGN and L1_CACHE_SHIFT values"

#include <asm/cachetype.h>

#define L1_CACHE_SHIFT		7

#define L1_CACHE_SHIFT		6

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

/*

 * Memory returned by kmalloc() may be used for DMA, so we must make

 * sure that all such allocations are cache aligned. Otherwise,

 * unrelated code may cause parts of the buffer to be read into the

 * cache before the transfer is done, causing old data to be seen by

 * the CPU.

 * sure that all such allocations are aligned to the maximum *known*

 * cache line size on ARMv8 systems. Otherwise, unrelated code may

 * cause parts of the buffer to be read into the cache before the

 * transfer is done, causing old data to be seen by the CPU.

 */

#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

#define ARCH_DMA_MINALIGN	(128)

#ifndef __ASSEMBLY__

	if (!cwg)

		pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",

			cls);

	if (L1_CACHE_BYTES < cls)

		pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",

			L1_CACHE_BYTES, cls);

	if (ARCH_DMA_MINALIGN < cls)

		pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",

			ARCH_DMA_MINALIGN, cls);

}

static bool __maybe_unused