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Commit 19740f9d authored by Gaurav Kohli's avatar Gaurav Kohli Committed by Gerrit - the friendly Code Review server
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soc: qcom: pil-q6v5: Update the reset sequence for qdspv62.1.2/1.5 



Update the reset sequence to read each write while enabling QDSP6 memory
bank one at a time. This will make sure whether write is complete or not.
Also add logs during Mss shutdown, It will help to debug Mss restart
and shutdown case.

Change-Id: I9f2cb058a7e59b573fc64662ee7b5bff49b18ea7
Signed-off-by: default avatarGaurav Kohli <gkohli@codeaurora.org>
parent 3162449f

drivers/soc/qcom/pil-msa.c

+1 −0
Original line number Diff line number Diff line
@@ -278,6 +278,7 @@ int pil_mss_shutdown(struct pil_desc *pil) 
	struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);

	int ret = 0;



	dev_info(pil->dev, "MSS is shutting down\n");

	if (drv->axi_halt_base) {

		pil_q6v5_halt_axi_port(pil,

			drv->axi_halt_base + MSS_Q6_HALT_BASE);

drivers/soc/qcom/pil-q6v5.c

+2 −0
Original line number Diff line number Diff line
@@ -512,6 +512,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
			val |= BIT(i);

			writel_relaxed(val, drv->reg_base +

					QDSP6V6SS_MEM_PWR_CTL);

			val = readl_relaxed(drv->reg_base +

					QDSP6V6SS_MEM_PWR_CTL);

			/*

			 * Wait for 1us for both memory peripheral and

			 * data array to turn on.