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Commit 17505518 authored by Gilad Landau's avatar Gilad Landau Committed by Kyle Yan
Browse files

msm: ipa3: Move IPA RAM mapping to DTS file 



Use DTS configuration file to initialize IPA memory partitions
in order to allow per target configuration decoupled from code.

Change-Id: If770b9315807e51e46cd94dec6234ef186cf4fcb
CRs-Fixed: 1022125
Signed-off-by: default avatarGilad Landau <glandau@codeaurora.org>
parent 13e4f13f

Documentation/devicetree/bindings/platform/msm/ipa.txt

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ IPA node: 
                   "bam-irq" - string to identify the IPA BAM interrupt.

                   "a2-bam-irq" - string to identify the A2 BAM interrupt.

- qcom,ipa-hw-ver: Specifies the IPA hardware version.

- qcom,ipa-ram-mmap: An array of unsigned integers representing addresses and

                     sizes which are used by the driver to access IPA RAM.



Optional:

drivers/platform/msm/ipa/ipa_v3/ipa.c

+9 −1
Original line number Diff line number Diff line
@@ -2128,7 +2128,7 @@ int _ipa_init_sram_v3_0(void) 
		return -ENOMEM;

	}



	/* Consult with ipa_ram_mmap.h on the location of the CANARY values */

	/* Consult with ipa_i.h on the location of the CANARY values */

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_hash_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_hash_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio,
@@ -4040,6 +4040,13 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, 
		goto fail_bind;

	}



	result = ipa3_init_mem_partition(ipa_dev->of_node);

	if (result) {

		IPAERR(":ipa3_init_mem_partition failed!\n");

		result = -ENODEV;

		goto fail_init_mem_partition;

	}



	if (ipa3_bus_scale_table) {

		IPADBG("Use bus scaling info from device tree\n");

		ipa3_ctx->ctrl->msm_bus_data_ptr = ipa3_bus_scale_table;
@@ -4490,6 +4497,7 @@ fail_ipahal: 
	ipa3_bus_scale_table = NULL;

fail_bus_reg:

	ipahal_destroy();

fail_init_mem_partition:

fail_bind:

	kfree(ipa3_ctx->ctrl);

fail_mem_ctrl:

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+153 −71
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
#include <linux/platform_device.h>

#include <linux/firmware.h>

#include "ipa_hw_defs.h"

#include "ipa_ram_mmap.h"

#include "ipa_qmi_service.h"

#include "../ipa_api.h"

#include "ipahal/ipahal_reg.h"
@@ -94,6 +93,10 @@ 
#define WLAN3_CONS_RX_EP  17

#define WLAN4_CONS_RX_EP  18



#define IPA_RAM_NAT_OFST    0

#define IPA_RAM_NAT_SIZE    0

#define IPA_MEM_CANARY_VAL 0xdeadbeef



#define IPA_STATS



#ifdef IPA_STATS
@@ -1520,77 +1523,155 @@ struct ipa3_plat_drv_res { 
	bool tethered_flow_control;

};



/**

 * struct ipa3_mem_partition - represents IPA RAM Map as read from DTS

 * Order and type of members should not be changed without a suitable change

 * to DTS file or the code that reads it.

 *

 * IPA v3.0 SRAM memory layout:

 * +-------------------------+

 * |    UC INFO              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM HDR              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | MODEM PROC CTX          |

 * +-------------------------+

 * | APPS PROC CTX           |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM MEM              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 */

struct ipa3_mem_partition {

	u16 ofst_start;

	u16 nat_ofst;

	u16 nat_size;

	u16 v4_flt_hash_ofst;

	u16 v4_flt_hash_size;

	u16 v4_flt_hash_size_ddr;

	u16 v4_flt_nhash_ofst;

	u16 v4_flt_nhash_size;

	u16 v4_flt_nhash_size_ddr;

	u16 v6_flt_hash_ofst;

	u16 v6_flt_hash_size;

	u16 v6_flt_hash_size_ddr;

	u16 v6_flt_nhash_ofst;

	u16 v6_flt_nhash_size;

	u16 v6_flt_nhash_size_ddr;

	u16 v4_rt_num_index;

	u16 v4_modem_rt_index_lo;

	u16 v4_modem_rt_index_hi;

	u16 v4_apps_rt_index_lo;

	u16 v4_apps_rt_index_hi;

	u16 v4_rt_hash_ofst;

	u16 v4_rt_hash_size;

	u16 v4_rt_hash_size_ddr;

	u16 v4_rt_nhash_ofst;

	u16 v4_rt_nhash_size;

	u16 v4_rt_nhash_size_ddr;

	u16 v6_rt_num_index;

	u16 v6_modem_rt_index_lo;

	u16 v6_modem_rt_index_hi;

	u16 v6_apps_rt_index_lo;

	u16 v6_apps_rt_index_hi;

	u16 v6_rt_hash_ofst;

	u16 v6_rt_hash_size;

	u16 v6_rt_hash_size_ddr;

	u16 v6_rt_nhash_ofst;

	u16 v6_rt_nhash_size;

	u16 v6_rt_nhash_size_ddr;

	u16 modem_hdr_ofst;

	u16 modem_hdr_size;

	u16 apps_hdr_ofst;

	u16 apps_hdr_size;

	u16 apps_hdr_size_ddr;

	u16 modem_hdr_proc_ctx_ofst;

	u16 modem_hdr_proc_ctx_size;

	u16 apps_hdr_proc_ctx_ofst;

	u16 apps_hdr_proc_ctx_size;

	u16 apps_hdr_proc_ctx_size_ddr;

	u16 modem_comp_decomp_ofst;

	u16 modem_comp_decomp_size;

	u16 modem_ofst;

	u16 modem_size;

	u16 apps_v4_flt_hash_ofst;

	u16 apps_v4_flt_hash_size;

	u16 apps_v4_flt_nhash_ofst;

	u16 apps_v4_flt_nhash_size;

	u16 apps_v6_flt_hash_ofst;

	u16 apps_v6_flt_hash_size;

	u16 apps_v6_flt_nhash_ofst;

	u16 apps_v6_flt_nhash_size;

	u16 uc_info_ofst;

	u16 uc_info_size;

	u16 end_ofst;

	u16 apps_v4_rt_hash_ofst;

	u16 apps_v4_rt_hash_size;

	u16 apps_v4_rt_nhash_ofst;

	u16 apps_v4_rt_nhash_size;

	u16 apps_v6_rt_hash_ofst;

	u16 apps_v6_rt_hash_size;

	u16 apps_v6_rt_nhash_ofst;

	u16 apps_v6_rt_nhash_size;

	u32 ofst_start;

	u32 nat_ofst;

	u32 nat_size;

	u32 v4_flt_hash_ofst;

	u32 v4_flt_hash_size;

	u32 v4_flt_hash_size_ddr;

	u32 v4_flt_nhash_ofst;

	u32 v4_flt_nhash_size;

	u32 v4_flt_nhash_size_ddr;

	u32 v6_flt_hash_ofst;

	u32 v6_flt_hash_size;

	u32 v6_flt_hash_size_ddr;

	u32 v6_flt_nhash_ofst;

	u32 v6_flt_nhash_size;

	u32 v6_flt_nhash_size_ddr;

	u32 v4_rt_num_index;

	u32 v4_modem_rt_index_lo;

	u32 v4_modem_rt_index_hi;

	u32 v4_apps_rt_index_lo;

	u32 v4_apps_rt_index_hi;

	u32 v4_rt_hash_ofst;

	u32 v4_rt_hash_size;

	u32 v4_rt_hash_size_ddr;

	u32 v4_rt_nhash_ofst;

	u32 v4_rt_nhash_size;

	u32 v4_rt_nhash_size_ddr;

	u32 v6_rt_num_index;

	u32 v6_modem_rt_index_lo;

	u32 v6_modem_rt_index_hi;

	u32 v6_apps_rt_index_lo;

	u32 v6_apps_rt_index_hi;

	u32 v6_rt_hash_ofst;

	u32 v6_rt_hash_size;

	u32 v6_rt_hash_size_ddr;

	u32 v6_rt_nhash_ofst;

	u32 v6_rt_nhash_size;

	u32 v6_rt_nhash_size_ddr;

	u32 modem_hdr_ofst;

	u32 modem_hdr_size;

	u32 apps_hdr_ofst;

	u32 apps_hdr_size;

	u32 apps_hdr_size_ddr;

	u32 modem_hdr_proc_ctx_ofst;

	u32 modem_hdr_proc_ctx_size;

	u32 apps_hdr_proc_ctx_ofst;

	u32 apps_hdr_proc_ctx_size;

	u32 apps_hdr_proc_ctx_size_ddr;

	u32 modem_comp_decomp_ofst;

	u32 modem_comp_decomp_size;

	u32 modem_ofst;

	u32 modem_size;

	u32 apps_v4_flt_hash_ofst;

	u32 apps_v4_flt_hash_size;

	u32 apps_v4_flt_nhash_ofst;

	u32 apps_v4_flt_nhash_size;

	u32 apps_v6_flt_hash_ofst;

	u32 apps_v6_flt_hash_size;

	u32 apps_v6_flt_nhash_ofst;

	u32 apps_v6_flt_nhash_size;

	u32 uc_info_ofst;

	u32 uc_info_size;

	u32 end_ofst;

	u32 apps_v4_rt_hash_ofst;

	u32 apps_v4_rt_hash_size;

	u32 apps_v4_rt_nhash_ofst;

	u32 apps_v4_rt_nhash_size;

	u32 apps_v6_rt_hash_ofst;

	u32 apps_v6_rt_hash_size;

	u32 apps_v6_rt_nhash_ofst;

	u32 apps_v6_rt_nhash_size;

};



struct ipa3_controller {
@@ -1999,6 +2080,7 @@ void ipa3_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size); 
#else

#define IPA_DUMP_BUFF(base, phy_base, size)

#endif

int ipa3_init_mem_partition(struct device_node *dev_node);

int ipa3_controller_static_bind(struct ipa3_controller *controller,

		enum ipa_hw_type ipa_hw_type);

int ipa3_cfg_route(struct ipahal_reg_route *route);

drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c

+0 −1
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ 
#include <linux/vmalloc.h>



#include "ipa_qmi_service.h"

#include "ipa_ram_mmap.h"



#define IPA_Q6_SVC_VERS 1

#define IPA_A5_SVC_VERS 1

drivers/platform/msm/ipa/ipa_v3/ipa_ram_mmap.h

deleted100644 → 0
+0 −307
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _IPA_RAM_MMAP_H_

#define _IPA_RAM_MMAP_H_



/*

 * This header defines the memory map of the IPA RAM (not all SRAM is

 * available for SW use)

 * In case of restricted bytes the actual starting address will be

 * advanced by the number of needed bytes

 */



#define IPA_RAM_NAT_OFST    0

#define IPA_RAM_NAT_SIZE    0



#define IPA_MEM_RAM_V6_RT_HASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V6_RT_NHASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V4_RT_HASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V4_RT_NHASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V6_FLT_HASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V6_FLT_NHASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V4_FLT_HASH_SIZE_DDR 16384

#define IPA_MEM_RAM_V4_FLT_NHASH_SIZE_DDR 16384

#define IPA_MEM_RAM_HDR_PROC_CTX_SIZE_DDR 0



#define IPA_MEM_CANARY_SIZE 4

#define IPA_MEM_CANARY_VAL 0xdeadbeef



#define IPA_MEM_RAM_MODEM_NETWORK_STATS_SIZE 256





/*

 * IPA v3.0 SRAM memory layout:

 * +-------------------------+

 * |    UC INFO              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V6 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM HDR              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | MODEM PROC CTX          |

 * +-------------------------+

 * | APPS PROC CTX           |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * |  MODEM MEM              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 */



#define IPA_MEM_v3_0_RAM_UC_MEM_SIZE 128

#define IPA_MEM_v3_0_RAM_UC_INFO_OFST IPA_MEM_v3_0_RAM_UC_MEM_SIZE

#define IPA_MEM_v3_0_RAM_UC_INFO_SIZE 512



/* uC info 4B aligned */

#if (IPA_MEM_v3_0_RAM_UC_INFO_OFST & 3)

#error uC info is not 4B aligned

#endif



#define IPA_MEM_v3_0_RAM_OFST_START (IPA_MEM_v3_0_RAM_UC_INFO_OFST + \

	IPA_MEM_v3_0_RAM_UC_INFO_SIZE)



#define IPA_MEM_v3_0_RAM_V4_FLT_HASH_OFST (IPA_MEM_v3_0_RAM_OFST_START + \

	2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_FLT_HASH_SIZE 120



/* V4 filtering hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_FLT_HASH_OFST & 7)

#error V4 filtering hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V4_FLT_NHASH_OFST \

	(IPA_MEM_v3_0_RAM_V4_FLT_HASH_OFST + \

	IPA_MEM_v3_0_RAM_V4_FLT_HASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_FLT_NHASH_SIZE 120



/* V4 filtering non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_FLT_NHASH_OFST & 7)

#error V4 filtering non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_FLT_HASH_OFST \

	(IPA_MEM_v3_0_RAM_V4_FLT_NHASH_OFST + \

	IPA_MEM_v3_0_RAM_V4_FLT_NHASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_FLT_HASH_SIZE 120



/* V6 filtering hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_FLT_HASH_OFST & 7)

#error V6 filtering hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_FLT_NHASH_OFST \

	(IPA_MEM_v3_0_RAM_V6_FLT_HASH_OFST + \

	IPA_MEM_v3_0_RAM_V6_FLT_HASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_FLT_NHASH_SIZE 120



/* V6 filtering non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_FLT_NHASH_OFST & 7)

#error V6 filtering header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V4_RT_NUM_INDEX 15

#define IPA_MEM_v3_0_V4_MODEM_RT_INDEX_LO 0

#define IPA_MEM_v3_0_V4_MODEM_RT_INDEX_HI 7

#define IPA_MEM_v3_0_V4_APPS_RT_INDEX_LO \

	(IPA_MEM_v3_0_V4_MODEM_RT_INDEX_HI + 1)

#define IPA_MEM_v3_0_V4_APPS_RT_INDEX_HI \

	(IPA_MEM_v3_0_RAM_V4_RT_NUM_INDEX - 1)



#define IPA_MEM_v3_0_RAM_V4_RT_HASH_OFST \

	(IPA_MEM_v3_0_RAM_V6_FLT_NHASH_OFST + \

	IPA_MEM_v3_0_RAM_V6_FLT_NHASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_RT_HASH_SIZE \

	(IPA_MEM_v3_0_RAM_V4_RT_NUM_INDEX * 8)



/* V4 routing hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_RT_HASH_OFST & 7)

#error V4 routing hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V4_RT_NHASH_OFST \

	(IPA_MEM_v3_0_RAM_V4_RT_HASH_OFST + \

	IPA_MEM_v3_0_RAM_V4_RT_HASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_RT_NHASH_SIZE \

	(IPA_MEM_v3_0_RAM_V4_RT_NUM_INDEX * 8)



/* V4 routing non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_RT_NHASH_OFST & 7)

#error V4 routing non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_RT_NUM_INDEX 15

#define IPA_MEM_v3_0_V6_MODEM_RT_INDEX_LO 0

#define IPA_MEM_v3_0_V6_MODEM_RT_INDEX_HI 7

#define IPA_MEM_v3_0_V6_APPS_RT_INDEX_LO \

	(IPA_MEM_v3_0_V6_MODEM_RT_INDEX_HI + 1)

#define IPA_MEM_v3_0_V6_APPS_RT_INDEX_HI \

	(IPA_MEM_v3_0_RAM_V6_RT_NUM_INDEX - 1)



#define IPA_MEM_v3_0_RAM_V6_RT_HASH_OFST \

	(IPA_MEM_v3_0_RAM_V4_RT_NHASH_OFST + \

	IPA_MEM_v3_0_RAM_V4_RT_NHASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_RT_HASH_SIZE \

	(IPA_MEM_v3_0_RAM_V6_RT_NUM_INDEX * 8)



/* V6 routing hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_RT_HASH_OFST & 7)

#error V6 routing hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_RT_NHASH_OFST \

	(IPA_MEM_v3_0_RAM_V6_RT_HASH_OFST + \

	IPA_MEM_v3_0_RAM_V6_RT_HASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_RT_NHASH_SIZE \

	(IPA_MEM_v3_0_RAM_V6_RT_NUM_INDEX * 8)



/* V6 routing non-hashable header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_RT_NHASH_OFST & 7)

#error V6 routing non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_MODEM_HDR_OFST \

	(IPA_MEM_v3_0_RAM_V6_RT_NHASH_OFST + \

	IPA_MEM_v3_0_RAM_V6_RT_NHASH_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_MODEM_HDR_SIZE 320



/* header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_MODEM_HDR_OFST & 7)

#error header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_APPS_HDR_OFST (IPA_MEM_v3_0_RAM_MODEM_HDR_OFST + \

	IPA_MEM_v3_0_RAM_MODEM_HDR_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_HDR_SIZE 0



/* header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_APPS_HDR_OFST & 7)

#error header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_OFST \

	(IPA_MEM_v3_0_RAM_APPS_HDR_OFST + IPA_MEM_v3_0_RAM_APPS_HDR_SIZE + \

	2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_SIZE 512



/* header processing context table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_OFST & 7)

#error header processing context table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_OFST \

	(IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_OFST + \

	IPA_MEM_v3_0_RAM_MODEM_HDR_PROC_CTX_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_SIZE 512



/* header processing context table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_OFST & 7)

#error header processing context table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_MODEM_OFST (IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_OFST + \

	IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_MODEM_SIZE 5156



/* modem memory is 8B aligned */

#if (IPA_MEM_v3_0_RAM_MODEM_OFST & 7)

#error modem memory is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_APPS_V4_FLT_HASH_OFST (IPA_MEM_v3_0_RAM_MODEM_OFST + \

	IPA_MEM_v3_0_RAM_MODEM_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_V4_FLT_HASH_SIZE 0



#define IPA_MEM_v3_0_RAM_APPS_V4_FLT_NHASH_OFST \

	(IPA_MEM_v3_0_RAM_APPS_V4_FLT_HASH_OFST + \

	IPA_MEM_v3_0_RAM_APPS_V4_FLT_HASH_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_V4_FLT_NHASH_SIZE 0



#define IPA_MEM_v3_0_RAM_APPS_V6_FLT_HASH_OFST \

	(IPA_MEM_v3_0_RAM_APPS_V4_FLT_NHASH_OFST + \

	IPA_MEM_v3_0_RAM_APPS_V4_FLT_NHASH_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_V6_FLT_HASH_SIZE 0



#define IPA_MEM_v3_0_RAM_APPS_V6_FLT_NHASH_OFST \

	(IPA_MEM_v3_0_RAM_APPS_V6_FLT_HASH_OFST + \

	IPA_MEM_v3_0_RAM_APPS_V6_FLT_HASH_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_V6_FLT_NHASH_SIZE 0



#define IPA_MEM_v3_0_RAM_END_OFST (IPA_MEM_v3_0_RAM_APPS_V6_FLT_NHASH_OFST + \

	IPA_MEM_v3_0_RAM_APPS_V6_FLT_NHASH_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_V4_RT_HASH_OFST IPA_MEM_v3_0_RAM_END_OFST

#define IPA_MEM_v3_0_RAM_APPS_V4_RT_HASH_SIZE 0

#define IPA_MEM_v3_0_RAM_APPS_V4_RT_NHASH_OFST IPA_MEM_v3_0_RAM_END_OFST

#define IPA_MEM_v3_0_RAM_APPS_V4_RT_NHASH_SIZE 0

#define IPA_MEM_v3_0_RAM_APPS_V6_RT_HASH_OFST IPA_MEM_v3_0_RAM_END_OFST

#define IPA_MEM_v3_0_RAM_APPS_V6_RT_HASH_SIZE 0

#define IPA_MEM_v3_0_RAM_APPS_V6_RT_NHASH_OFST IPA_MEM_v3_0_RAM_END_OFST

#define IPA_MEM_v3_0_RAM_APPS_V6_RT_NHASH_SIZE 0

#define IPA_MEM_v3_0_RAM_HDR_SIZE_DDR 2048



#endif /* _IPA_RAM_MMAP_H_ */