Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 172a5317 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Kyle Yan
Browse files

clk: qcom: rpmcc: Add rpm clock data for msm8996 



Add all RPM clock data for msm8996 family of devices

ToDo: Adapt to changes needed for RPM over GLINK against
RPM over SMD that the driver currently supports

Change-Id: Ib095af601a4f03d866cf94c8e277d04630abb42b
Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 5bfbe957

drivers/clk/qcom/clk-smd-rpm.c

+75 −0
Original line number Diff line number Diff line
@@ -462,8 +462,83 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 
	.num_clks = ARRAY_SIZE(msm8916_clks),

};



/* msm8996 */

DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);

DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,

		   QCOM_SMD_RPM_MMAXI_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);

DEFINE_CLK_SMD_RPM_BRANCH(msm8996, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);

DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,

			  QCOM_SMD_RPM_AGGR_CLK, 0, 1000);

DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,

			  QCOM_SMD_RPM_AGGR_CLK, 1, 1000);

DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_ao, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_ao, 0xc);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_ao, 0xc);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);



static struct clk_smd_rpm *msm8996_clks[] = {

	[RPM_XO_CLK_SRC] = &msm8996_cxo,

	[RPM_XO_A_CLK_SRC] = &msm8996_cxo_a,

	[RPM_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,

	[RPM_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,

	[RPM_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,

	[RPM_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,

	[RPM_PCNOC_CLK] = &msm8996_pcnoc_clk,

	[RPM_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk,

	[RPM_SNOC_CLK] = &msm8996_snoc_clk,

	[RPM_SNOC_A_CLK] = &msm8996_snoc_a_clk,

	[RPM_CNOC_CLK] = &msm8996_cnoc_clk,

	[RPM_CNOC_A_CLK] = &msm8996_cnoc_a_clk,

	[RPM_BIMC_CLK] = &msm8996_bimc_clk,

	[RPM_BIMC_A_CLK] = &msm8996_bimc_a_clk,

	[RPM_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,

	[RPM_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,

	[RPM_IPA_CLK] = &msm8996_ipa_clk,

	[RPM_IPA_A_CLK] = &msm8996_ipa_a_clk,

	[RPM_CE1_CLK] = &msm8996_ce1_clk,

	[RPM_CE1_A_CLK] = &msm8996_ce1_a_clk,

	[RPM_QDSS_CLK] = &msm8996_qdss_clk,

	[RPM_QDSS_A_CLK] = &msm8996_qdss_a_clk,

	[RPM_LN_BB_CLK] = &msm8996_ln_bb_clk,

	[RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk,

	[RPM_DIV_CLK1] = &msm8996_div_clk1,

	[RPM_DIV_CLK1_AO] = &msm8996_div_clk1_ao,

	[RPM_DIV_CLK2] = &msm8996_div_clk2,

	[RPM_DIV_CLK2_AO] = &msm8996_div_clk2_ao,

	[RPM_DIV_CLK3] = &msm8996_div_clk3,

	[RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao,

	[RPM_BB_CLK1_PIN] = &msm8996_bb_clk1_pin,

	[RPM_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin,

	[RPM_BB_CLK2_PIN] = &msm8996_bb_clk2_pin,

	[RPM_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin,

	[RPM_RF_CLK1_PIN] = &msm8996_rf_clk1_pin,

	[RPM_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin,

	[RPM_RF_CLK2_PIN] = &msm8996_rf_clk2_pin,

	[RPM_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin,

};



static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {

	.clks = msm8996_clks,

	.num_clks = ARRAY_SIZE(msm8996_clks),

};



static const struct of_device_id rpm_smd_clk_match_table[] = {

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},

	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996},

	{ }

};

MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);

include/dt-bindings/clock/qcom,rpmcc.h

+36 −0
Original line number Diff line number Diff line
@@ -65,5 +65,41 @@ 
#define RPM_SMD_RF_CLK1_A_PIN			23

#define RPM_SMD_RF_CLK2_PIN				24

#define RPM_SMD_RF_CLK2_A_PIN			25

#define RPM_BB_CLK1				10

#define RPM_BB_CLK1_A				11

#define RPM_BB_CLK2				12

#define RPM_BB_CLK2_A				13

#define RPM_RF_CLK1				14

#define RPM_RF_CLK1_A				15

#define RPM_RF_CLK2				16

#define RPM_RF_CLK2_A				17

#define RPM_BB_CLK1_PIN				18

#define RPM_BB_CLK1_A_PIN			19

#define RPM_BB_CLK2_PIN				20

#define RPM_BB_CLK2_A_PIN			21

#define RPM_RF_CLK1_PIN				22

#define RPM_RF_CLK1_A_PIN			23

#define RPM_RF_CLK2_PIN				24

#define RPM_RF_CLK2_A_PIN			25

#define RPM_AGGR1_NOC_CLK			26

#define RPM_AGGR1_NOC_A_CLK			27

#define RPM_AGGR2_NOC_CLK			28

#define RPM_AGGR2_NOC_A_CLK			29

#define RPM_CNOC_CLK				30

#define RPM_CNOC_A_CLK				31

#define RPM_MMAXI_CLK				32

#define RPM_MMAXI_A_CLK				33

#define RPM_IPA_CLK				34

#define RPM_IPA_A_CLK				35

#define RPM_CE1_CLK				36

#define RPM_CE1_A_CLK				37

#define RPM_DIV_CLK1				38

#define RPM_DIV_CLK1_AO				39

#define RPM_DIV_CLK2				40

#define RPM_DIV_CLK2_AO				41

#define RPM_DIV_CLK3				42

#define RPM_DIV_CLK3_AO				43

#define RPM_LN_BB_CLK				44

#define RPM_LN_BB_A_CLK				45



#endif

include/linux/soc/qcom/smd-rpm.h

+4 −0
Original line number Diff line number Diff line
@@ -26,6 +26,10 @@ struct qcom_smd_rpm; 
#define QCOM_SMD_RPM_SMPB	0x62706d73

#define QCOM_SMD_RPM_SPDM	0x63707362

#define QCOM_SMD_RPM_VSA	0x00617376

#define QCOM_SMD_RPM_MMAXI_CLK	0x69786d6d

#define QCOM_SMD_RPM_IPA_CLK	0x617069

#define QCOM_SMD_RPM_CE_CLK	0x6563

#define QCOM_SMD_RPM_AGGR_CLK	0x72676761



int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,

		       int state,