powerpc/85xx: Updates to P4080DS device tree (169296b3) · Commits · e / devices / android_kernel_sony_msm8998

arch/powerpc/boot/dts/p4080ds.dts

+222 −107

Original line number	Original line	Diff line number	Diff line
	@@ -3,10 +3,33 @@
	*		*
	* Copyright 2009-2011 Freescale Semiconductor Inc.		* Copyright 2009-2011 Freescale Semiconductor Inc.
	*		*
	* This program is free software; you can redistribute it and/or modify it		* Redistribution and use in source and binary forms, with or without
	* under the terms of the GNU General Public License as published by the		* modification, are permitted provided that the following conditions are met:
	* Free Software Foundation; either version 2 of the License, or (at your		* * Redistributions of source code must retain the above copyright
	* option) any later version.		* notice, this list of conditions and the following disclaimer.
			* * Redistributions in binary form must reproduce the above copyright
			* notice, this list of conditions and the following disclaimer in the
			* documentation and/or other materials provided with the distribution.
			* * Neither the name of Freescale Semiconductor nor the
			* names of its contributors may be used to endorse or promote products
			* derived from this software without specific prior written permission.
			*
			*
			* ALTERNATIVELY, this software may be distributed under the terms of the
			* GNU General Public License ("GPL") as published by the Free Software
			* Foundation, either version 2 of that License or (at your option) any
			* later version.
			*
			* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
			* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
			* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
			* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
			* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
			* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
			* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
			* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
			* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
			* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	*/		*/

	/dts-v1/;		/dts-v1/;
	@@ -16,6 +39,7 @@
	compatible = "fsl,P4080DS";		compatible = "fsl,P4080DS";
	#address-cells = <2>;		#address-cells = <2>;
	#size-cells = <2>;		#size-cells = <2>;
			interrupt-parent = <&mpic>;

	aliases {		aliases {
	ccsr = &soc;		ccsr = &soc;
	@@ -32,6 +56,9 @@
	dma0 = &dma0;		dma0 = &dma0;
	dma1 = &dma1;		dma1 = &dma1;
	sdhc = &sdhc;		sdhc = &sdhc;
			msi0 = &msi0;
			msi1 = &msi1;
			msi2 = &msi2;

	crypto = &crypto;		crypto = &crypto;
	sec_jr0 = &sec_jr0;		sec_jr0 = &sec_jr0;
	@@ -56,6 +83,7 @@
	reg = <0>;		reg = <0>;
	next-level-cache = <&L2_0>;		next-level-cache = <&L2_0>;
	L2_0: l2-cache {		L2_0: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu1: PowerPC,4080@1 {		cpu1: PowerPC,4080@1 {
	@@ -63,6 +91,7 @@
	reg = <1>;		reg = <1>;
	next-level-cache = <&L2_1>;		next-level-cache = <&L2_1>;
	L2_1: l2-cache {		L2_1: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu2: PowerPC,4080@2 {		cpu2: PowerPC,4080@2 {
	@@ -70,6 +99,7 @@
	reg = <2>;		reg = <2>;
	next-level-cache = <&L2_2>;		next-level-cache = <&L2_2>;
	L2_2: l2-cache {		L2_2: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu3: PowerPC,4080@3 {		cpu3: PowerPC,4080@3 {
	@@ -77,6 +107,7 @@
	reg = <3>;		reg = <3>;
	next-level-cache = <&L2_3>;		next-level-cache = <&L2_3>;
	L2_3: l2-cache {		L2_3: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu4: PowerPC,4080@4 {		cpu4: PowerPC,4080@4 {
	@@ -84,6 +115,7 @@
	reg = <4>;		reg = <4>;
	next-level-cache = <&L2_4>;		next-level-cache = <&L2_4>;
	L2_4: l2-cache {		L2_4: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu5: PowerPC,4080@5 {		cpu5: PowerPC,4080@5 {
	@@ -91,6 +123,7 @@
	reg = <5>;		reg = <5>;
	next-level-cache = <&L2_5>;		next-level-cache = <&L2_5>;
	L2_5: l2-cache {		L2_5: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu6: PowerPC,4080@6 {		cpu6: PowerPC,4080@6 {
	@@ -98,6 +131,7 @@
	reg = <6>;		reg = <6>;
	next-level-cache = <&L2_6>;		next-level-cache = <&L2_6>;
	L2_6: l2-cache {		L2_6: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	cpu7: PowerPC,4080@7 {		cpu7: PowerPC,4080@7 {
	@@ -105,6 +139,7 @@
	reg = <7>;		reg = <7>;
	next-level-cache = <&L2_7>;		next-level-cache = <&L2_7>;
	L2_7: l2-cache {		L2_7: l2-cache {
			next-level-cache = <&cpc>;
	};		};
	};		};
	};		};
	@@ -121,6 +156,11 @@
	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
	reg = <0xf 0xfe000000 0 0x00001000>;		reg = <0xf 0xfe000000 0 0x00001000>;

			soc-sram-error {
			compatible = "fsl,soc-sram-error";
			interrupts = <16 2 1 29>;
			};

	corenet-law@0 {		corenet-law@0 {
	compatible = "fsl,corenet-law";		compatible = "fsl,corenet-law";
	reg = <0x0 0x1000>;		reg = <0x0 0x1000>;
	@@ -128,42 +168,132 @@
	};		};

	memory-controller@8000 {		memory-controller@8000 {
	compatible = "fsl,p4080-memory-controller";		compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
	reg = <0x8000 0x1000>;		reg = <0x8000 0x1000>;
	interrupt-parent = <&mpic>;		interrupts = <16 2 1 23>;
	interrupts = <0x12 2>;
	};		};

	memory-controller@9000 {		memory-controller@9000 {
	compatible = "fsl,p4080-memory-controller";		compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
	reg = <0x9000 0x1000>;		reg = <0x9000 0x1000>;
	interrupt-parent = <&mpic>;		interrupts = <16 2 1 22>;
	interrupts = <0x12 2>;		};

			cpc: l3-cache-controller@10000 {
			compatible = "fsl,p4080-l3-cache-controller", "cache";
			reg = <0x10000 0x1000
			0x11000 0x1000>;
			interrupts = <16 2 1 27
			16 2 1 26>;
	};		};

	corenet-cf@18000 {		corenet-cf@18000 {
	compatible = "fsl,corenet-cf";		compatible = "fsl,corenet-cf";
	reg = <0x18000 0x1000>;		reg = <0x18000 0x1000>;
			interrupts = <16 2 1 31>;
	fsl,ccf-num-csdids = <32>;		fsl,ccf-num-csdids = <32>;
	fsl,ccf-num-snoopids = <32>;		fsl,ccf-num-snoopids = <32>;
	};		};

	iommu@20000 {		iommu@20000 {
	compatible = "fsl,p4080-pamu";		compatible = "fsl,pamu-v1.0", "fsl,pamu";
	reg = <0x20000 0x10000>;		reg = <0x20000 0x5000>;
	interrupts = <24 2>;		interrupts = <
	interrupt-parent = <&mpic>;		24 2 0 0
			16 2 1 30>;
	};		};

	mpic: pic@40000 {		mpic: pic@40000 {
			clock-frequency = <0>;
	interrupt-controller;		interrupt-controller;
	#address-cells = <0>;		#address-cells = <0>;
	#interrupt-cells = <2>;		#interrupt-cells = <4>;
	reg = <0x40000 0x40000>;		reg = <0x40000 0x40000>;
	compatible = "chrp,open-pic";		compatible = "fsl,mpic", "chrp,open-pic";
	device_type = "open-pic";		device_type = "open-pic";
	};		};

			msi0: msi@41600 {
			compatible = "fsl,mpic-msi";
			reg = <0x41600 0x200>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
			0xe0 0 0 0
			0xe1 0 0 0
			0xe2 0 0 0
			0xe3 0 0 0
			0xe4 0 0 0
			0xe5 0 0 0
			0xe6 0 0 0
			0xe7 0 0 0>;
			};

			msi1: msi@41800 {
			compatible = "fsl,mpic-msi";
			reg = <0x41800 0x200>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
			0xe8 0 0 0
			0xe9 0 0 0
			0xea 0 0 0
			0xeb 0 0 0
			0xec 0 0 0
			0xed 0 0 0
			0xee 0 0 0
			0xef 0 0 0>;
			};

			msi2: msi@41a00 {
			compatible = "fsl,mpic-msi";
			reg = <0x41a00 0x200>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
			0xf0 0 0 0
			0xf1 0 0 0
			0xf2 0 0 0
			0xf3 0 0 0
			0xf4 0 0 0
			0xf5 0 0 0
			0xf6 0 0 0
			0xf7 0 0 0>;
			};

			guts: global-utilities@e0000 {
			compatible = "fsl,qoriq-device-config-1.0";
			reg = <0xe0000 0xe00>;
			fsl,has-rstcr;
			#sleep-cells = <1>;
			fsl,liodn-bits = <12>;
			};

			pins: global-utilities@e0e00 {
			compatible = "fsl,qoriq-pin-control-1.0";
			reg = <0xe0e00 0x200>;
			#sleep-cells = <2>;
			};

			clockgen: global-utilities@e1000 {
			compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
			reg = <0xe1000 0x1000>;
			clock-frequency = <0>;
			};

			rcpm: global-utilities@e2000 {
			compatible = "fsl,qoriq-rcpm-1.0";
			reg = <0xe2000 0x1000>;
			#sleep-cells = <1>;
			};

			sfp: sfp@e8000 {
			compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
			reg = <0xe8000 0x1000>;
			};

			serdes: serdes@ea000 {
			compatible = "fsl,p4080-serdes";
			reg = <0xea000 0x1000>;
			};

	dma0: dma@100300 {		dma0: dma@100300 {
	#address-cells = <1>;		#address-cells = <1>;
	#size-cells = <1>;		#size-cells = <1>;
	@@ -176,32 +306,28 @@
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x0 0x80>;		reg = <0x0 0x80>;
	cell-index = <0>;		cell-index = <0>;
	interrupt-parent = <&mpic>;		interrupts = <28 2 0 0>;
	interrupts = <28 2>;
	};		};
	dma-channel@80 {		dma-channel@80 {
	compatible = "fsl,p4080-dma-channel",		compatible = "fsl,p4080-dma-channel",
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x80 0x80>;		reg = <0x80 0x80>;
	cell-index = <1>;		cell-index = <1>;
	interrupt-parent = <&mpic>;		interrupts = <29 2 0 0>;
	interrupts = <29 2>;
	};		};
	dma-channel@100 {		dma-channel@100 {
	compatible = "fsl,p4080-dma-channel",		compatible = "fsl,p4080-dma-channel",
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x100 0x80>;		reg = <0x100 0x80>;
	cell-index = <2>;		cell-index = <2>;
	interrupt-parent = <&mpic>;		interrupts = <30 2 0 0>;
	interrupts = <30 2>;
	};		};
	dma-channel@180 {		dma-channel@180 {
	compatible = "fsl,p4080-dma-channel",		compatible = "fsl,p4080-dma-channel",
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x180 0x80>;		reg = <0x180 0x80>;
	cell-index = <3>;		cell-index = <3>;
	interrupt-parent = <&mpic>;		interrupts = <31 2 0 0>;
	interrupts = <31 2>;
	};		};
	};		};

	@@ -217,32 +343,28 @@
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x0 0x80>;		reg = <0x0 0x80>;
	cell-index = <0>;		cell-index = <0>;
	interrupt-parent = <&mpic>;		interrupts = <32 2 0 0>;
	interrupts = <32 2>;
	};		};
	dma-channel@80 {		dma-channel@80 {
	compatible = "fsl,p4080-dma-channel",		compatible = "fsl,p4080-dma-channel",
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x80 0x80>;		reg = <0x80 0x80>;
	cell-index = <1>;		cell-index = <1>;
	interrupt-parent = <&mpic>;		interrupts = <33 2 0 0>;
	interrupts = <33 2>;
	};		};
	dma-channel@100 {		dma-channel@100 {
	compatible = "fsl,p4080-dma-channel",		compatible = "fsl,p4080-dma-channel",
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x100 0x80>;		reg = <0x100 0x80>;
	cell-index = <2>;		cell-index = <2>;
	interrupt-parent = <&mpic>;		interrupts = <34 2 0 0>;
	interrupts = <34 2>;
	};		};
	dma-channel@180 {		dma-channel@180 {
	compatible = "fsl,p4080-dma-channel",		compatible = "fsl,p4080-dma-channel",
	"fsl,eloplus-dma-channel";		"fsl,eloplus-dma-channel";
	reg = <0x180 0x80>;		reg = <0x180 0x80>;
	cell-index = <3>;		cell-index = <3>;
	interrupt-parent = <&mpic>;		interrupts = <35 2 0 0>;
	interrupts = <35 2>;
	};		};
	};		};

	@@ -251,8 +373,7 @@
	#size-cells = <0>;		#size-cells = <0>;
	compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";		compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
	reg = <0x110000 0x1000>;		reg = <0x110000 0x1000>;
	interrupts = <53 0x2>;		interrupts = <53 0x2 0 0>;
	interrupt-parent = <&mpic>;
	fsl,espi-num-chipselects = <4>;		fsl,espi-num-chipselects = <4>;

	flash@0 {		flash@0 {
	@@ -286,10 +407,10 @@
	sdhc: sdhc@114000 {		sdhc: sdhc@114000 {
	compatible = "fsl,p4080-esdhc", "fsl,esdhc";		compatible = "fsl,p4080-esdhc", "fsl,esdhc";
	reg = <0x114000 0x1000>;		reg = <0x114000 0x1000>;
	interrupts = <48 2>;		interrupts = <48 2 0 0>;
	interrupt-parent = <&mpic>;
	voltage-ranges = <3300 3300>;		voltage-ranges = <3300 3300>;
	sdhci,auto-cmd12;		sdhci,auto-cmd12;
			clock-frequency = <0>;
	};		};

	i2c@118000 {		i2c@118000 {
	@@ -298,8 +419,7 @@
	cell-index = <0>;		cell-index = <0>;
	compatible = "fsl-i2c";		compatible = "fsl-i2c";
	reg = <0x118000 0x100>;		reg = <0x118000 0x100>;
	interrupts = <38 2>;		interrupts = <38 2 0 0>;
	interrupt-parent = <&mpic>;
	dfsrr;		dfsrr;
	};		};

	@@ -309,8 +429,7 @@
	cell-index = <1>;		cell-index = <1>;
	compatible = "fsl-i2c";		compatible = "fsl-i2c";
	reg = <0x118100 0x100>;		reg = <0x118100 0x100>;
	interrupts = <38 2>;		interrupts = <38 2 0 0>;
	interrupt-parent = <&mpic>;
	dfsrr;		dfsrr;
	eeprom@51 {		eeprom@51 {
	compatible = "at24,24c256";		compatible = "at24,24c256";
	@@ -323,8 +442,7 @@
	rtc@68 {		rtc@68 {
	compatible = "dallas,ds3232";		compatible = "dallas,ds3232";
	reg = <0x68>;		reg = <0x68>;
	interrupts = <0 0x1>;		interrupts = <0x1 0x1 0 0>;
	interrupt-parent = <&mpic>;
	};		};
	};		};

	@@ -334,8 +452,7 @@
	cell-index = <2>;		cell-index = <2>;
	compatible = "fsl-i2c";		compatible = "fsl-i2c";
	reg = <0x119000 0x100>;		reg = <0x119000 0x100>;
	interrupts = <39 2>;		interrupts = <39 2 0 0>;
	interrupt-parent = <&mpic>;
	dfsrr;		dfsrr;
	};		};

	@@ -345,8 +462,7 @@
	cell-index = <3>;		cell-index = <3>;
	compatible = "fsl-i2c";		compatible = "fsl-i2c";
	reg = <0x119100 0x100>;		reg = <0x119100 0x100>;
	interrupts = <39 2>;		interrupts = <39 2 0 0>;
	interrupt-parent = <&mpic>;
	dfsrr;		dfsrr;
	};		};

	@@ -356,8 +472,7 @@
	compatible = "ns16550";		compatible = "ns16550";
	reg = <0x11c500 0x100>;		reg = <0x11c500 0x100>;
	clock-frequency = <0>;		clock-frequency = <0>;
	interrupts = <36 2>;		interrupts = <36 2 0 0>;
	interrupt-parent = <&mpic>;
	};		};

	serial1: serial@11c600 {		serial1: serial@11c600 {
	@@ -366,8 +481,7 @@
	compatible = "ns16550";		compatible = "ns16550";
	reg = <0x11c600 0x100>;		reg = <0x11c600 0x100>;
	clock-frequency = <0>;		clock-frequency = <0>;
	interrupts = <36 2>;		interrupts = <36 2 0 0>;
	interrupt-parent = <&mpic>;
	};		};

	serial2: serial@11d500 {		serial2: serial@11d500 {
	@@ -376,8 +490,7 @@
	compatible = "ns16550";		compatible = "ns16550";
	reg = <0x11d500 0x100>;		reg = <0x11d500 0x100>;
	clock-frequency = <0>;		clock-frequency = <0>;
	interrupts = <37 2>;		interrupts = <37 2 0 0>;
	interrupt-parent = <&mpic>;
	};		};

	serial3: serial@11d600 {		serial3: serial@11d600 {
	@@ -386,15 +499,13 @@
	compatible = "ns16550";		compatible = "ns16550";
	reg = <0x11d600 0x100>;		reg = <0x11d600 0x100>;
	clock-frequency = <0>;		clock-frequency = <0>;
	interrupts = <37 2>;		interrupts = <37 2 0 0>;
	interrupt-parent = <&mpic>;
	};		};

	gpio0: gpio@130000 {		gpio0: gpio@130000 {
	compatible = "fsl,p4080-gpio";		compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
	reg = <0x130000 0x1000>;		reg = <0x130000 0x1000>;
	interrupts = <55 2>;		interrupts = <55 2 0 0>;
	interrupt-parent = <&mpic>;
	#gpio-cells = <2>;		#gpio-cells = <2>;
	gpio-controller;		gpio-controller;
	};		};
	@@ -405,8 +516,7 @@
	reg = <0x210000 0x1000>;		reg = <0x210000 0x1000>;
	#address-cells = <1>;		#address-cells = <1>;
	#size-cells = <0>;		#size-cells = <0>;
	interrupt-parent = <&mpic>;		interrupts = <44 0x2 0 0>;
	interrupts = <44 0x2>;
	phy_type = "ulpi";		phy_type = "ulpi";
	};		};

	@@ -416,8 +526,7 @@
	reg = <0x211000 0x1000>;		reg = <0x211000 0x1000>;
	#address-cells = <1>;		#address-cells = <1>;
	#size-cells = <0>;		#size-cells = <0>;
	interrupt-parent = <&mpic>;		interrupts = <45 0x2 0 0>;
	interrupts = <45 0x2>;
	dr_mode = "host";		dr_mode = "host";
	phy_type = "ulpi";		phy_type = "ulpi";
	};		};
	@@ -429,34 +538,34 @@
	reg = <0x300000 0x10000>;		reg = <0x300000 0x10000>;
	ranges = <0 0x300000 0x10000>;		ranges = <0 0x300000 0x10000>;
	interrupt-parent = <&mpic>;		interrupt-parent = <&mpic>;
	interrupts = <92 2>;		interrupts = <92 2 0 0>;

	sec_jr0: jr@1000 {		sec_jr0: jr@1000 {
	compatible = "fsl,sec-v4.0-job-ring";		compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x1000 0x1000>;		reg = <0x1000 0x1000>;
	interrupt-parent = <&mpic>;		interrupt-parent = <&mpic>;
	interrupts = <88 2>;		interrupts = <88 2 0 0>;
	};		};

	sec_jr1: jr@2000 {		sec_jr1: jr@2000 {
	compatible = "fsl,sec-v4.0-job-ring";		compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x2000 0x1000>;		reg = <0x2000 0x1000>;
	interrupt-parent = <&mpic>;		interrupt-parent = <&mpic>;
	interrupts = <89 2>;		interrupts = <89 2 0 0>;
	};		};

	sec_jr2: jr@3000 {		sec_jr2: jr@3000 {
	compatible = "fsl,sec-v4.0-job-ring";		compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x3000 0x1000>;		reg = <0x3000 0x1000>;
	interrupt-parent = <&mpic>;		interrupt-parent = <&mpic>;
	interrupts = <90 2>;		interrupts = <90 2 0 0>;
	};		};

	sec_jr3: jr@4000 {		sec_jr3: jr@4000 {
	compatible = "fsl,sec-v4.0-job-ring";		compatible = "fsl,sec-v4.0-job-ring";
	reg = <0x4000 0x1000>;		reg = <0x4000 0x1000>;
	interrupt-parent = <&mpic>;		interrupt-parent = <&mpic>;
	interrupts = <91 2>;		interrupts = <91 2 0 0>;
	};		};

	rtic@6000 {		rtic@6000 {
	@@ -492,7 +601,7 @@
	compatible = "fsl,sec-v4.0-mon";		compatible = "fsl,sec-v4.0-mon";
	reg = <0x314000 0x1000>;		reg = <0x314000 0x1000>;
	interrupt-parent = <&mpic>;		interrupt-parent = <&mpic>;
	interrupts = <93 2>;		interrupts = <93 2 0 0>;
	};		};
	};		};

	@@ -501,17 +610,21 @@
	#size-cells = <2>;		#size-cells = <2>;
	compatible = "fsl,rapidio-delta";		compatible = "fsl,rapidio-delta";
	reg = <0xf 0xfe0c0000 0 0x20000>;		reg = <0xf 0xfe0c0000 0 0x20000>;
	ranges = <0 0 0xf 0xf5000000 0 0x01000000>;		ranges = <0 0 0xc 0x20000000 0 0x01000000>;
	interrupt-parent = <&mpic>;		interrupts = <
	/* err_irq bell_outb_irq bell_inb_irq		16 2 1 11 /* err_irq */
	msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */		56 2 0 0 /* bell_outb_irq */
	interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;		57 2 0 0 /* bell_inb_irq */
			60 2 0 0 /* msg1_tx_irq */
			61 2 0 0 /* msg1_rx_irq */
			62 2 0 0 /* msg2_tx_irq */
			63 2 0 0>; /* msg2_rx_irq */
	};		};

	localbus@ffe124000 {		localbus@ffe124000 {
	compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";		compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
	reg = <0xf 0xfe124000 0 0x1000>;		reg = <0xf 0xfe124000 0 0x1000>;
	interrupts = <25 2>;		interrupts = <25 2 0 0>;
	#address-cells = <2>;		#address-cells = <2>;
	#size-cells = <1>;		#size-cells = <1>;

	@@ -528,7 +641,6 @@
	pci0: pcie@ffe200000 {		pci0: pcie@ffe200000 {
	compatible = "fsl,p4080-pcie";		compatible = "fsl,p4080-pcie";
	device_type = "pci";		device_type = "pci";
	#interrupt-cells = <1>;
	#size-cells = <2>;		#size-cells = <2>;
	#address-cells = <3>;		#address-cells = <3>;
	reg = <0xf 0xfe200000 0 0x1000>;		reg = <0xf 0xfe200000 0 0x1000>;
	@@ -536,22 +648,23 @@
	ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
	0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;		0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
	clock-frequency = <0x1fca055>;		clock-frequency = <0x1fca055>;
	interrupt-parent = <&mpic>;		fsl,msi = <&msi0>;
	interrupts = <16 2>;		interrupts = <16 2 1 15>;

	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 40 1
	0000 0 0 2 &mpic 1 1
	0000 0 0 3 &mpic 2 1
	0000 0 0 4 &mpic 3 1
	>;
	pcie@0 {		pcie@0 {
	reg = <0 0 0 0 0>;		reg = <0 0 0 0 0>;
			#interrupt-cells = <1>;
	#size-cells = <2>;		#size-cells = <2>;
	#address-cells = <3>;		#address-cells = <3>;
	device_type = "pci";		device_type = "pci";
			interrupts = <16 2 1 15>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 40 1 0 0
			0000 0 0 2 &mpic 1 1 0 0
			0000 0 0 3 &mpic 2 1 0 0
			0000 0 0 4 &mpic 3 1 0 0
			>;
	ranges = <0x02000000 0 0xe0000000		ranges = <0x02000000 0 0xe0000000
	0x02000000 0 0xe0000000		0x02000000 0 0xe0000000
	0 0x20000000		0 0x20000000
	@@ -565,7 +678,6 @@
	pci1: pcie@ffe201000 {		pci1: pcie@ffe201000 {
	compatible = "fsl,p4080-pcie";		compatible = "fsl,p4080-pcie";
	device_type = "pci";		device_type = "pci";
	#interrupt-cells = <1>;
	#size-cells = <2>;		#size-cells = <2>;
	#address-cells = <3>;		#address-cells = <3>;
	reg = <0xf 0xfe201000 0 0x1000>;		reg = <0xf 0xfe201000 0 0x1000>;
	@@ -573,21 +685,23 @@
	ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
	0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;		0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
	clock-frequency = <0x1fca055>;		clock-frequency = <0x1fca055>;
	interrupt-parent = <&mpic>;		fsl,msi = <&msi1>;
	interrupts = <16 2>;		interrupts = <16 2 1 14>;
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 41 1
	0000 0 0 2 &mpic 5 1
	0000 0 0 3 &mpic 6 1
	0000 0 0 4 &mpic 7 1
	>;
	pcie@0 {		pcie@0 {
	reg = <0 0 0 0 0>;		reg = <0 0 0 0 0>;
			#interrupt-cells = <1>;
	#size-cells = <2>;		#size-cells = <2>;
	#address-cells = <3>;		#address-cells = <3>;
	device_type = "pci";		device_type = "pci";
			interrupts = <16 2 1 14>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 41 1 0 0
			0000 0 0 2 &mpic 5 1 0 0
			0000 0 0 3 &mpic 6 1 0 0
			0000 0 0 4 &mpic 7 1 0 0
			>;
	ranges = <0x02000000 0 0xe0000000		ranges = <0x02000000 0 0xe0000000
	0x02000000 0 0xe0000000		0x02000000 0 0xe0000000
	0 0x20000000		0 0x20000000
	@@ -601,7 +715,6 @@
	pci2: pcie@ffe202000 {		pci2: pcie@ffe202000 {
	compatible = "fsl,p4080-pcie";		compatible = "fsl,p4080-pcie";
	device_type = "pci";		device_type = "pci";
	#interrupt-cells = <1>;
	#size-cells = <2>;		#size-cells = <2>;
	#address-cells = <3>;		#address-cells = <3>;
	reg = <0xf 0xfe202000 0 0x1000>;		reg = <0xf 0xfe202000 0 0x1000>;
	@@ -609,21 +722,23 @@
	ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
	0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;		0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
	clock-frequency = <0x1fca055>;		clock-frequency = <0x1fca055>;
	interrupt-parent = <&mpic>;		fsl,msi = <&msi2>;
	interrupts = <16 2>;		interrupts = <16 2 1 13>;
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 42 1
	0000 0 0 2 &mpic 9 1
	0000 0 0 3 &mpic 10 1
	0000 0 0 4 &mpic 11 1
	>;
	pcie@0 {		pcie@0 {
	reg = <0 0 0 0 0>;		reg = <0 0 0 0 0>;
			#interrupt-cells = <1>;
	#size-cells = <2>;		#size-cells = <2>;
	#address-cells = <3>;		#address-cells = <3>;
	device_type = "pci";		device_type = "pci";
			interrupts = <16 2 1 13>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 42 1 0 0
			0000 0 0 2 &mpic 9 1 0 0
			0000 0 0 3 &mpic 10 1 0 0
			0000 0 0 4 &mpic 11 1 0 0
			>;
	ranges = <0x02000000 0 0xe0000000		ranges = <0x02000000 0 0xe0000000
	0x02000000 0 0xe0000000		0x02000000 0 0xe0000000
	0 0x20000000		0 0x20000000