Merge "msm: camera: sensor: Change REFGEN for DPHY CLK/DATA to internal bias" (15f0386b) · Commits · e / devices / android_kernel_sony_msm8998

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -100,6 +100,8 @@ struct csiphy_reg_3ph_parms_t csiphy_v5_0_1_3ph = {
		{0x38, 0xFE},
		{0x81c, 0x2},
		{0x700, 0x80},
		{0x724, 0x04},
		{0x024, 0x04},
		};

		struct csiphy_settings_t csiphy_combo_mode_v5_0_1 = {

+2 −0

Original line number	Diff line number	Diff line
		@@ -101,6 +101,8 @@ struct csiphy_reg_3ph_parms_t csiphy_v5_0_3ph = {
		{0x38, 0xFE},
		{0x81c, 0x6},
		{0x700, 0x80},
		{0x724, 0x04},
		{0x024, 0x04},
		};

		struct csiphy_settings_t csiphy_combo_mode_v5_0 = {

+16 −2

Original line number	Diff line number	Diff line
		@@ -684,14 +684,20 @@ static int msm_csiphy_2phase_lane_config_v50(
		csiphybase + csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnn_ctrl15.addr + offset);
		if (mask == CLOCK_LANE)
		if (mask == CLOCK_LANE) {
		msm_camera_io_w(csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnck_ctrl0.data,
		csiphybase + csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnck_ctrl0.addr);
		else
		msm_camera_io_w(csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnck_ctrl9.data,
		csiphybase + csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnck_ctrl9.addr);
		} else {
		msm_camera_io_w(csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnn_ctrl0.data,
		@@ -699,6 +705,14 @@ static int msm_csiphy_2phase_lane_config_v50(
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnn_ctrl0.addr +
		offset);
		msm_camera_io_w(csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnn_ctrl9.data,
		csiphybase + csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnn_ctrl9.addr +
		offset);
		}
		msm_camera_io_w(csiphy_dev->ctrl_reg->
		csiphy_3ph_reg.
		mipi_csiphy_2ph_lnn_cfg1.data,

+2 −0

Original line number	Diff line number	Diff line
		@@ -142,6 +142,8 @@ struct csiphy_reg_3ph_parms_t {
		struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl14;
		struct csiphy_reg_t mipi_csiphy_3ph_cmn_ctrl7_cphy;
		struct csiphy_reg_t mipi_csiphy_2ph_lnck_ctrl0;
		struct csiphy_reg_t mipi_csiphy_2ph_lnck_ctrl9;
		struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl9;
		};

		struct csiphy_ctrl_t {