Loading Documentation/devicetree/bindings/arm/cache.txt +8 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,14 @@ This document provides the device tree bindings for ARM architected caches. bindings of power controller specified by the phandle [5]. - qcom,dump-size Usage: Optional Value type: <integer> Definition: The memory size needed to contain a copy of the cache data and associated tag ram. size = nways * nsets * (bytes per cache line + bytes tag ram per line) Example(dual-cluster big.LITTLE system 32-bit) cpus { Loading Loading
Documentation/devicetree/bindings/arm/cache.txt +8 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,14 @@ This document provides the device tree bindings for ARM architected caches. bindings of power controller specified by the phandle [5]. - qcom,dump-size Usage: Optional Value type: <integer> Definition: The memory size needed to contain a copy of the cache data and associated tag ram. size = nways * nsets * (bytes per cache line + bytes tag ram per line) Example(dual-cluster big.LITTLE system 32-bit) cpus { Loading