Merge "ASoC: wcd9330: Update driver for 12.288MHz clock support" (102a3b4b) · Commits · e / devices / android_kernel_sony_msm8998

sound/soc/codecs/wcd9330.c

+8 −2

Original line number	Diff line number	Diff line
		@@ -8472,6 +8472,9 @@ static int tomtom_post_reset_cb(struct wcd9xxx *wcd9xxx)
		wcd9xxx_mbhc_deinit(&tomtom->mbhc);
		tomtom->mbhc_started = false;

		if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_12P288MHZ)
		rco_clk_rate = TOMTOM_MCLK_CLK_12P288MHZ;
		else
		rco_clk_rate = TOMTOM_MCLK_CLK_9P6MHZ;

		ret = wcd9xxx_mbhc_init(&tomtom->mbhc, &tomtom->resmgr, codec,
		@@ -8814,6 +8817,9 @@ static int tomtom_codec_probe(struct snd_soc_codec *codec)
		tomtom->clsh_d.is_dynamic_vdd_cp = false;
		wcd9xxx_clsh_init(&tomtom->clsh_d, &tomtom->resmgr);

		if (wcd9xxx->mclk_rate == TOMTOM_MCLK_CLK_12P288MHZ)
		rco_clk_rate = TOMTOM_MCLK_CLK_12P288MHZ;
		else
		rco_clk_rate = TOMTOM_MCLK_CLK_9P6MHZ;

		tomtom->fw_data = kzalloc(sizeof(*(tomtom->fw_data)), GFP_KERNEL);

sound/soc/codecs/wcd9xxx-resmgr.c

+34 −14

Original line number	Diff line number	Diff line
		/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -430,13 +430,20 @@ int wcd9xxx_resmgr_enable_config_mode(struct wcd9xxx_resmgr *resmgr, int enable)
		if (enable) {
		snd_soc_update_bits(codec, WCD9XXX_A_RC_OSC_FREQ, 0x10, 0);
		/* bandgap mode to fast */
		if (resmgr->pdata->mclk_rate == WCD9XXX_MCLK_CLK_12P288MHZ)
		/* Set current value to 200nA for 12.288MHz clock */
		snd_soc_write(codec, WCD9XXX_A_BIAS_OSC_BG_CTL, 0x37);
		else
		snd_soc_write(codec, WCD9XXX_A_BIAS_OSC_BG_CTL, 0x17);

		usleep_range(5, 10);
		snd_soc_update_bits(codec, WCD9XXX_A_RC_OSC_FREQ, 0x80, 0x80);
		snd_soc_update_bits(codec, WCD9XXX_A_RC_OSC_TEST, 0x80, 0x80);
		usleep_range(10, 20);
		snd_soc_update_bits(codec, WCD9XXX_A_RC_OSC_TEST, 0x80, 0);
		usleep_range(10000, 10100);

		if (resmgr->pdata->mclk_rate != WCD9XXX_MCLK_CLK_12P288MHZ)
		snd_soc_update_bits(codec, WCD9XXX_A_CLK_BUFF_EN1,
		0x08, 0x08);
		} else {
		@@ -476,13 +483,24 @@ static void wcd9xxx_enable_clock_block(struct wcd9xxx_resmgr *resmgr,
		/* 1ms sleep required after BG enabled */
		usleep_range(1000, 1100);

		snd_soc_update_bits(codec, TOMTOM_A_RCO_CTRL, 0x18, 0x10);
		valr = snd_soc_read(codec, TOMTOM_A_QFUSE_DATA_OUT0) & (0x04);
		valr1 = snd_soc_read(codec, TOMTOM_A_QFUSE_DATA_OUT1) & (0x08);
		if (resmgr->pdata->mclk_rate == WCD9XXX_MCLK_CLK_12P288MHZ) {
		/*
		* Set RCO clock rate as 12.288MHz rate explicitly
		* as the Qfuse values are incorrect for this rate
		*/
		snd_soc_update_bits(codec, TOMTOM_A_RCO_CTRL,
		0x50, 0x50);
		} else {
		snd_soc_update_bits(codec, TOMTOM_A_RCO_CTRL,
		0x18, 0x10);
		valr = snd_soc_read(codec,
		TOMTOM_A_QFUSE_DATA_OUT0) & (0x04);
		valr1 = snd_soc_read(codec,
		TOMTOM_A_QFUSE_DATA_OUT1) & (0x08);
		valr = (valr >> 1) \| (valr1 >> 3);
		snd_soc_update_bits(codec, TOMTOM_A_RCO_CTRL, 0x60,
		valw[valr] << 5);

		}
		snd_soc_update_bits(codec, TOMTOM_A_RCO_CTRL, 0x80, 0x80);

		do {
		@@ -611,6 +629,8 @@ void wcd9xxx_resmgr_get_clk_block(struct wcd9xxx_resmgr *resmgr,
		wcd9xxx_resmgr_notifier_call(resmgr,
		WCD9XXX_EVENT_PRE_RCO_ON);
		/* CLK MUX to RCO */
		if (resmgr->pdata->mclk_rate !=
		WCD9XXX_MCLK_CLK_12P288MHZ)
		snd_soc_update_bits(codec,
		WCD9XXX_A_CLK_BUFF_EN1,
		0x08, 0x08);