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Commit 0f0f8c61 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

ARM: dts: msm: add DT properties for dynamic refresh for SDM660/SDM630 



Add the DT properties in DSI controller/PLL nodes/memory nodes which
are needed for supporting dynamic refresh feature for SDM660/SDM630.

Change-Id: Iccfaf219705de28eb4bd721987075eab09b0120f
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent c025f2d3

arch/arm/boot/dts/qcom/sdm630-mdss-pll.dtsi

+4 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -19,8 +19,9 @@ 
		#clock-cells = <1>;



		reg = <0xc994400 0x588>,

		      <0xc8c2300 0x8>;

		reg-names = "pll_base", "gdsc_base";

		      <0xc8c2300 0x8>,

		      <0xc994200 0x98>;

		reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";



		gdsc-supply = <&gdsc_mdss>;

arch/arm/boot/dts/qcom/sdm630-mdss.dtsi

+12 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -359,10 +359,19 @@ 
				 <&clock_mmss MMSS_MDSS_ESC0_CLK>,

				 <&clock_mmss BYTE0_CLK_SRC>,

				 <&clock_mmss PCLK0_CLK_SRC>,

				 <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>;

				 <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>,

				 <&mdss_dsi0_pll BYTE0_MUX_CLK>,

				 <&mdss_dsi0_pll PIX0_MUX_CLK>,

				 <&mdss_dsi0_pll BYTE0_SRC_CLK>,

				 <&mdss_dsi0_pll PIX0_SRC_CLK>,

				 <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>,

				 <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>;

			clock-names = "byte_clk", "pixel_clk", "core_clk",

				"byte_clk_rcg", "pixel_clk_rcg",

				"byte_intf_clk";

				"byte_intf_clk", "pll_byte_clk_mux",

				"pll_pixel_clk_mux", "pll_byte_clk_src",

				"pll_pixel_clk_src", "pll_shadow_byte_clk_src",

				"pll_shadow_pixel_clk_src";



			qcom,platform-strength-ctrl = [ff 06

							ff 06

arch/arm/boot/dts/qcom/sdm630.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -406,9 +406,14 @@ 
		};



		cont_splash_mem: splash_region@9d400000 {

			reg = <0x0 0x9d400000 0x0 0x02400000>;

			reg = <0x0 0x9d400000 0x0 0x23ff000>;

			label = "cont_splash_mem";

		};



		dfps_data_mem: dfps_data_mem@0x9f7ff000 {

		       reg = <0 0x9f7ff000 0 0x00001000>;

		       label = "dfps_data_mem";

		};

	};



	bluetooth: bt_wcn3990 {

arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi

+8 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -19,8 +19,9 @@ 
		#clock-cells = <1>;



		reg = <0xc994400 0x588>,

		      <0xc8c2300 0x8>;

		reg-names = "pll_base", "gdsc_base";

		      <0xc8c2300 0x8>,

		      <0xc994200 0x98>;

		reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";



		gdsc-supply = <&gdsc_mdss>;
@@ -29,6 +30,7 @@ 
		clock-rate = <0>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

		memory-region = <&dfps_data_mem>;



		qcom,platform-supply-entries {

			#address-cells = <1>;
@@ -54,8 +56,9 @@ 
		#clock-cells = <1>;



		reg = <0xc996400 0x588>,

		      <0xc8c2300 0x8>;

		reg-names = "pll_base", "gdsc_base";

		      <0xc8c2300 0x8>,

		      <0xc996200 0x98>;

		reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";



		gdsc-supply = <&gdsc_mdss>;

arch/arm/boot/dts/qcom/sdm660-mdss.dtsi

+23 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -382,10 +382,19 @@ 
				 <&clock_mmss MMSS_MDSS_ESC0_CLK>,

				 <&clock_mmss BYTE0_CLK_SRC>,

				 <&clock_mmss PCLK0_CLK_SRC>,

				 <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>;

				 <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>,

				 <&mdss_dsi0_pll BYTE0_MUX_CLK>,

				 <&mdss_dsi0_pll PIX0_MUX_CLK>,

				 <&mdss_dsi0_pll BYTE0_SRC_CLK>,

				 <&mdss_dsi0_pll PIX0_SRC_CLK>,

				 <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>,

				 <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>;

			clock-names = "byte_clk", "pixel_clk", "core_clk",

				"byte_clk_rcg", "pixel_clk_rcg",

				"byte_intf_clk";

				"byte_intf_clk", "pll_byte_clk_mux",

				"pll_pixel_clk_mux", "pll_byte_clk_src",

				"pll_pixel_clk_src", "pll_shadow_byte_clk_src",

				"pll_shadow_pixel_clk_src";



			qcom,null-insertion-enabled;

			qcom,platform-strength-ctrl = [ff 06
@@ -423,10 +432,19 @@ 
				 <&clock_mmss MMSS_MDSS_ESC1_CLK>,

				 <&clock_mmss BYTE1_CLK_SRC>,

				 <&clock_mmss PCLK1_CLK_SRC>,

				 <&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>;

				 <&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>,

				 <&mdss_dsi1_pll BYTE1_MUX_CLK>,

				 <&mdss_dsi1_pll PIX1_MUX_CLK>,

				 <&mdss_dsi1_pll BYTE1_SRC_CLK>,

				 <&mdss_dsi1_pll PIX1_SRC_CLK>,

				 <&mdss_dsi1_pll SHADOW_BYTE1_SRC_CLK>,

				 <&mdss_dsi1_pll SHADOW_PIX1_SRC_CLK>;

			clock-names = "byte_clk", "pixel_clk", "core_clk",

				"byte_clk_rcg", "pixel_clk_rcg",

				"byte_intf_clk";

				"byte_intf_clk", "pll_byte_clk_mux",

				"pll_pixel_clk_mux", "pll_byte_clk_src",

				"pll_pixel_clk_src", "pll_shadow_byte_clk_src",

				"pll_shadow_pixel_clk_src";



			qcom,null-insertion-enabled;

			qcom,platform-strength-ctrl = [ff 06