Loading drivers/clk/qcom/clk-smd-rpm.c +70 −23 Original line number Diff line number Diff line Loading @@ -551,6 +551,39 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5); /* Voter clocks */ static DEFINE_CLK_VOTER(mmssnoc_axi_clk, mmssnoc_axi_rpm_clk, 0); static DEFINE_CLK_VOTER(mmssnoc_axi_a_clk, mmssnoc_axi_rpm_a_clk, 0); static DEFINE_CLK_VOTER(mmssnoc_gds_clk, mmssnoc_axi_rpm_clk, 40000000); static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX); static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, pnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, pnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_pm_clk, pnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_sps_clk, pnoc_clk, 0); static DEFINE_CLK_VOTER(mmssnoc_a_clk_cpu_vote, mmssnoc_axi_rpm_a_clk, 19200000); /* Voter Branch clocks */ static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_ssc_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo); static struct clk_hw *msm8996_clks[] = { [RPM_XO_CLK_SRC] = &msm8996_cxo.hw, [RPM_XO_A_CLK_SRC] = &msm8996_cxo_a.hw, Loading Loading @@ -590,6 +623,31 @@ static struct clk_hw *msm8996_clks[] = { [RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao.hw, [RPM_LN_BB_CLK] = &msm8996_ln_bb_clk.hw, [RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk.hw, [MMSSNOC_AXI_CLK] = &mmssnoc_axi_clk.hw, [MMSSNOC_AXI_A_CLK] = &mmssnoc_axi_a_clk.hw, [MMSSNOC_GDS_CLK] = &mmssnoc_gds_clk.hw, [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, [BIMC_MSMBUS_A_CLK] = &bimc_msmbus_a_clk.hw, [CNOC_MSMBUS_CLK] = &cnoc_msmbus_clk.hw, [CNOC_MSMBUS_A_CLK] = &cnoc_msmbus_a_clk.hw, [PNOC_KEEPALIVE_A_CLK] = &pnoc_keepalive_a_clk.hw, [PNOC_MSMBUS_CLK] = &pnoc_msmbus_clk.hw, [PNOC_MSMBUS_A_CLK] = &pnoc_msmbus_a_clk.hw, [PNOC_PM_CLK] = &pnoc_pm_clk.hw, [PNOC_SPS_CLK] = &pnoc_sps_clk.hw, [MCD_CE1_CLK] = &mcd_ce1_clk.hw, [QCEDEV_CE1_CLK] = &qcedev_ce1_clk.hw, [QCRYPTO_CE1_CLK] = &qcrypto_ce1_clk.hw, [QSEECOM_CE1_CLK] = &qseecom_ce1_clk.hw, [SCM_CE1_CLK] = &scm_ce1_clk.hw, [SNOC_MSMBUS_CLK] = &snoc_msmbus_clk.hw, [SNOC_MSMBUS_A_CLK] = &snoc_msmbus_a_clk.hw, [CXO_DWC3_CLK] = &cxo_dwc3_clk.hw, [CXO_LPM_CLK] = &cxo_lpm_clk.hw, [CXO_OTG_CLK] = &cxo_otg_clk.hw, [CXO_PIL_LPASS_CLK] = &cxo_pil_lpass_clk.hw, [CXO_PIL_SSC_CLK] = &cxo_pil_ssc_clk.hw, [MMSSNOC_A_CLK_CPU_VOTE] = &mmssnoc_a_clk_cpu_vote.hw }; static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { Loading Loading @@ -627,26 +685,6 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, ln_bb_clk2_pin_ao, 0x2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin, ln_bb_clk3_pin_ao, 0x3); /* Voter clocks */ static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX); static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo); static struct clk_hw *msmfalcon_clks[] = { [RPM_XO_CLK_SRC] = &msmfalcon_cxo.hw, Loading Loading @@ -799,10 +837,19 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) if (ret) goto err; /* Keep an active vote on CXO in case no other driver votes for it */ if (is_8996) if (is_8996) { /* * Keep an active vote on CXO in case no other driver * votes for it. */ clk_prepare_enable(msm8996_cxo_a.hw.clk); else if (is_falcon) { /* Hold an active set vote for the pnoc_keepalive_a_clk */ clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000); clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk); clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk); } else if (is_falcon) { clk_prepare_enable(msmfalcon_cxo_a.hw.clk); /* Hold an active set vote for the cnoc_periph resource */ Loading include/dt-bindings/clock/qcom,rpmcc.h +1 −0 Original line number Diff line number Diff line Loading @@ -128,5 +128,6 @@ #define CXO_PIL_SSC_CLK 83 #define CXO_PIL_CDSP_CLK 84 #define CNOC_PERIPH_KEEPALIVE_A_CLK 85 #define MMSSNOC_A_CLK_CPU_VOTE 86 #endif Loading
drivers/clk/qcom/clk-smd-rpm.c +70 −23 Original line number Diff line number Diff line Loading @@ -551,6 +551,39 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5); /* Voter clocks */ static DEFINE_CLK_VOTER(mmssnoc_axi_clk, mmssnoc_axi_rpm_clk, 0); static DEFINE_CLK_VOTER(mmssnoc_axi_a_clk, mmssnoc_axi_rpm_a_clk, 0); static DEFINE_CLK_VOTER(mmssnoc_gds_clk, mmssnoc_axi_rpm_clk, 40000000); static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX); static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, pnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, pnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_pm_clk, pnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_sps_clk, pnoc_clk, 0); static DEFINE_CLK_VOTER(mmssnoc_a_clk_cpu_vote, mmssnoc_axi_rpm_a_clk, 19200000); /* Voter Branch clocks */ static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_ssc_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo); static struct clk_hw *msm8996_clks[] = { [RPM_XO_CLK_SRC] = &msm8996_cxo.hw, [RPM_XO_A_CLK_SRC] = &msm8996_cxo_a.hw, Loading Loading @@ -590,6 +623,31 @@ static struct clk_hw *msm8996_clks[] = { [RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao.hw, [RPM_LN_BB_CLK] = &msm8996_ln_bb_clk.hw, [RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk.hw, [MMSSNOC_AXI_CLK] = &mmssnoc_axi_clk.hw, [MMSSNOC_AXI_A_CLK] = &mmssnoc_axi_a_clk.hw, [MMSSNOC_GDS_CLK] = &mmssnoc_gds_clk.hw, [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, [BIMC_MSMBUS_A_CLK] = &bimc_msmbus_a_clk.hw, [CNOC_MSMBUS_CLK] = &cnoc_msmbus_clk.hw, [CNOC_MSMBUS_A_CLK] = &cnoc_msmbus_a_clk.hw, [PNOC_KEEPALIVE_A_CLK] = &pnoc_keepalive_a_clk.hw, [PNOC_MSMBUS_CLK] = &pnoc_msmbus_clk.hw, [PNOC_MSMBUS_A_CLK] = &pnoc_msmbus_a_clk.hw, [PNOC_PM_CLK] = &pnoc_pm_clk.hw, [PNOC_SPS_CLK] = &pnoc_sps_clk.hw, [MCD_CE1_CLK] = &mcd_ce1_clk.hw, [QCEDEV_CE1_CLK] = &qcedev_ce1_clk.hw, [QCRYPTO_CE1_CLK] = &qcrypto_ce1_clk.hw, [QSEECOM_CE1_CLK] = &qseecom_ce1_clk.hw, [SCM_CE1_CLK] = &scm_ce1_clk.hw, [SNOC_MSMBUS_CLK] = &snoc_msmbus_clk.hw, [SNOC_MSMBUS_A_CLK] = &snoc_msmbus_a_clk.hw, [CXO_DWC3_CLK] = &cxo_dwc3_clk.hw, [CXO_LPM_CLK] = &cxo_lpm_clk.hw, [CXO_OTG_CLK] = &cxo_otg_clk.hw, [CXO_PIL_LPASS_CLK] = &cxo_pil_lpass_clk.hw, [CXO_PIL_SSC_CLK] = &cxo_pil_ssc_clk.hw, [MMSSNOC_A_CLK_CPU_VOTE] = &mmssnoc_a_clk_cpu_vote.hw }; static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { Loading Loading @@ -627,26 +685,6 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, ln_bb_clk2_pin_ao, 0x2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin, ln_bb_clk3_pin_ao, 0x3); /* Voter clocks */ static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX); static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000); static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo); static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo); static struct clk_hw *msmfalcon_clks[] = { [RPM_XO_CLK_SRC] = &msmfalcon_cxo.hw, Loading Loading @@ -799,10 +837,19 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) if (ret) goto err; /* Keep an active vote on CXO in case no other driver votes for it */ if (is_8996) if (is_8996) { /* * Keep an active vote on CXO in case no other driver * votes for it. */ clk_prepare_enable(msm8996_cxo_a.hw.clk); else if (is_falcon) { /* Hold an active set vote for the pnoc_keepalive_a_clk */ clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000); clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk); clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk); } else if (is_falcon) { clk_prepare_enable(msmfalcon_cxo_a.hw.clk); /* Hold an active set vote for the cnoc_periph resource */ Loading
include/dt-bindings/clock/qcom,rpmcc.h +1 −0 Original line number Diff line number Diff line Loading @@ -128,5 +128,6 @@ #define CXO_PIL_SSC_CLK 83 #define CXO_PIL_CDSP_CLK 84 #define CNOC_PERIPH_KEEPALIVE_A_CLK 85 #define MMSSNOC_A_CLK_CPU_VOTE 86 #endif