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Commit 0df13b0b authored by Sathish Ambley's avatar Sathish Ambley
Browse files

ARM: dts: msm: Enable cache coherency for fastrpc devices on msmcobalt 



Enabled cache coherency for fastrpc devices by adding dma-coherent
flag.

Change-Id: I8ea271103c202cefdedae62f2717f1bee44c1d78
Acked-by: default avatarViswanatham Paduchuri <vpaduchu@qti.qualcomm.com>
Signed-off-by: default avatarSathish Ambley <sathishambley@codeaurora.org>
parent ba1f8794

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1186,41 +1186,49 @@ 
			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 2>;

			qcom,secure-context-bank;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb1 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 8>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb2 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 9>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb3 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 10>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb4 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 11>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb6 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 5>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb7 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 6>;

			dma-coherent;

		};

		qcom,msm_fastrpc_compute_cb8 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&lpass_q6_smmu 7>;

			dma-coherent;

		};

	};