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Commit 0b5fce48 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Ulf Hansson
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mmc: dw_mmc: exynos: move definitions to header file 



Move exynos related definition to header file. And this
also changes some of the registers name to match the standard
naming convention.

Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
[Alim: updated the commit message]
Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent a2a1fed8

drivers/mmc/host/dw_mmc-exynos.c

+6 −42
Original line number Diff line number Diff line
@@ -21,43 +21,7 @@ 


#include "dw_mmc.h"

#include "dw_mmc-pltfm.h"



#define NUM_PINS(x)			(x + 2)



#define SDMMC_CLKSEL			0x09C

#define SDMMC_CLKSEL64			0x0A8

#define SDMMC_CLKSEL_CCLK_SAMPLE(x)	(((x) & 7) << 0)

#define SDMMC_CLKSEL_CCLK_DRIVE(x)	(((x) & 7) << 16)

#define SDMMC_CLKSEL_CCLK_DIVIDER(x)	(((x) & 7) << 24)

#define SDMMC_CLKSEL_GET_DRV_WD3(x)	(((x) >> 16) & 0x7)

#define SDMMC_CLKSEL_TIMING(x, y, z)	(SDMMC_CLKSEL_CCLK_SAMPLE(x) |	\

					SDMMC_CLKSEL_CCLK_DRIVE(y) |	\

					SDMMC_CLKSEL_CCLK_DIVIDER(z))

#define SDMMC_CLKSEL_WAKEUP_INT		BIT(11)



#define EXYNOS4210_FIXED_CIU_CLK_DIV	2

#define EXYNOS4412_FIXED_CIU_CLK_DIV	4



/* Block number in eMMC */

#define DWMCI_BLOCK_NUM		0xFFFFFFFF



#define SDMMC_EMMCP_BASE	0x1000

#define SDMMC_MPSECURITY	(SDMMC_EMMCP_BASE + 0x0010)

#define SDMMC_MPSBEGIN0		(SDMMC_EMMCP_BASE + 0x0200)

#define SDMMC_MPSEND0		(SDMMC_EMMCP_BASE + 0x0204)

#define SDMMC_MPSCTRL0		(SDMMC_EMMCP_BASE + 0x020C)



/* SMU control bits */

#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)

#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)

#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)

#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)

#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)

#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)

#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)

#define DWMCI_MPSCTRL_VALID			BIT(0)



#define EXYNOS_CCLKIN_MIN	50000000	/* unit: HZ */

#include "dw_mmc-exynos.h"



/* Variations in Exynos specific dw-mshc controller */

enum dw_mci_exynos_type {
@@ -114,11 +78,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) 
	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {

		mci_writel(host, MPSBEGIN0, 0);

		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);

		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |

			   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |

			   DWMCI_MPSCTRL_VALID |

			   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);

		mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);

		mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |

			   SDMMC_MPSCTRL_NON_SECURE_READ_BIT |

			   SDMMC_MPSCTRL_VALID |

			   SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);

	}



	return 0;

drivers/mmc/host/dw_mmc-exynos.h

0 → 100644
+56 −0
Original line number Diff line number Diff line 
/*

 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver

 *

 * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef _DW_MMC_EXYNOS_H_

#define _DW_MMC_EXYNOS_H_



/* Extended Register's Offset */

#define SDMMC_CLKSEL			0x09C

#define SDMMC_CLKSEL64			0x0A8



/* CLKSEL register defines */

#define SDMMC_CLKSEL_CCLK_SAMPLE(x)	(((x) & 7) << 0)

#define SDMMC_CLKSEL_CCLK_DRIVE(x)	(((x) & 7) << 16)

#define SDMMC_CLKSEL_CCLK_DIVIDER(x)	(((x) & 7) << 24)

#define SDMMC_CLKSEL_GET_DRV_WD3(x)	(((x) >> 16) & 0x7)

#define SDMMC_CLKSEL_TIMING(x, y, z)	(SDMMC_CLKSEL_CCLK_SAMPLE(x) |	\

					 SDMMC_CLKSEL_CCLK_DRIVE(y) |	\

					 SDMMC_CLKSEL_CCLK_DIVIDER(z))

#define SDMMC_CLKSEL_WAKEUP_INT		BIT(11)



/* Protector Register */

#define SDMMC_EMMCP_BASE	0x1000

#define SDMMC_MPSECURITY	(SDMMC_EMMCP_BASE + 0x0010)

#define SDMMC_MPSBEGIN0		(SDMMC_EMMCP_BASE + 0x0200)

#define SDMMC_MPSEND0		(SDMMC_EMMCP_BASE + 0x0204)

#define SDMMC_MPSCTRL0		(SDMMC_EMMCP_BASE + 0x020C)



/* SMU control defines */

#define SDMMC_MPSCTRL_SECURE_READ_BIT		BIT(7)

#define SDMMC_MPSCTRL_SECURE_WRITE_BIT		BIT(6)

#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)

#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)

#define SDMMC_MPSCTRL_USE_FUSE_KEY		BIT(3)

#define SDMMC_MPSCTRL_ECB_MODE			BIT(2)

#define SDMMC_MPSCTRL_ENCRYPTION		BIT(1)

#define SDMMC_MPSCTRL_VALID			BIT(0)



/* Maximum number of Ending sector */

#define SDMMC_ENDING_SEC_NR_MAX	0xFFFFFFFF



/* Fixed clock divider */

#define EXYNOS4210_FIXED_CIU_CLK_DIV	2

#define EXYNOS4412_FIXED_CIU_CLK_DIV	4



/* Minimal required clock frequency for cclkin, unit: HZ */

#define EXYNOS_CCLKIN_MIN	50000000



#endif /* _DW_MMC_EXYNOS_H_ */