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Commit 0b5c5ed0 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Adjust CRC capture for pre-gen5/vlv 



Should work down to gen2. The #defines for the interrupt sources are
already there in PIPESTAT and are the same on all gmch platforms for
gen2 up to vlv.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1cf84bb6

drivers/gpu/drm/i915/i915_irq.c

+19 −9
Original line number Original line Diff line number Diff line
@@ -1249,21 +1249,31 @@ static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe) 
				I915_READ(PIPE_CRC_RES_5_IVB(pipe)));

				I915_READ(PIPE_CRC_RES_5_IVB(pipe)));

}

}





static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)

static void i9xx_pipe_crc_update(struct drm_device *dev, enum pipe pipe)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t res1, res2;



	if (INTEL_INFO(dev)->gen >= 3)

		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));

	else

		res1 = 0;



	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))

		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));

	else

		res2 = 0;





	display_pipe_crc_update(dev, pipe,

	display_pipe_crc_update(dev, pipe,

				I915_READ(PIPE_CRC_RES_RED_ILK(pipe)),

				I915_READ(PIPE_CRC_RES_RED(pipe)),

				I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),

				I915_READ(PIPE_CRC_RES_GREEN(pipe)),

				I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),

				I915_READ(PIPE_CRC_RES_BLUE(pipe)),

				I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),

				res1, res2);

				I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));

}

}

#else

#else

static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}

static inline void hsw_pipe_crc_update(struct drm_device *dev, int pipe) {}

static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}

static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}

static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}

static inline void i9xx_pipe_crc_update(struct drm_device *dev, int pipe) {}

#endif

#endif





/* The RPS events need forcewake, so we add them to a work queue and mask their

/* The RPS events need forcewake, so we add them to a work queue and mask their
@@ -1543,10 +1553,10 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 
			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");

			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");





	if (de_iir & DE_PIPEA_CRC_DONE)

	if (de_iir & DE_PIPEA_CRC_DONE)

		ilk_pipe_crc_update(dev, PIPE_A);

		i9xx_pipe_crc_update(dev, PIPE_A);





	if (de_iir & DE_PIPEB_CRC_DONE)

	if (de_iir & DE_PIPEB_CRC_DONE)

		ilk_pipe_crc_update(dev, PIPE_B);

		i9xx_pipe_crc_update(dev, PIPE_B);





	if (de_iir & DE_PLANEA_FLIP_DONE) {

	if (de_iir & DE_PLANEA_FLIP_DONE) {

		intel_prepare_page_flip(dev, 0);

		intel_prepare_page_flip(dev, 0);

drivers/gpu/drm/i915/i915_reg.h

+15 −15
Original line number Original line Diff line number Diff line
@@ -1858,11 +1858,11 @@ 
#define _PIPE_CRC_RES_4_A_IVB		0x60070

#define _PIPE_CRC_RES_4_A_IVB		0x60070

#define _PIPE_CRC_RES_5_A_IVB		0x60074

#define _PIPE_CRC_RES_5_A_IVB		0x60074





#define _PIPE_CRC_RES_RED_A_ILK		0x60060

#define _PIPE_CRC_RES_RED_A		(dev_priv->info->display_mmio_offset + 0x60060)

#define _PIPE_CRC_RES_GREEN_A_ILK	0x60064

#define _PIPE_CRC_RES_GREEN_A		(dev_priv->info->display_mmio_offset + 0x60064)

#define _PIPE_CRC_RES_BLUE_A_ILK	0x60068

#define _PIPE_CRC_RES_BLUE_A		(dev_priv->info->display_mmio_offset + 0x60068)

#define _PIPE_CRC_RES_RES1_A_ILK	0x6006c

#define _PIPE_CRC_RES_RES1_A_I915	(dev_priv->info->display_mmio_offset + 0x6006c)

#define _PIPE_CRC_RES_RES2_A_ILK	0x60080

#define _PIPE_CRC_RES_RES2_A_G4X	(dev_priv->info->display_mmio_offset + 0x60080)





/* Pipe B CRC regs */

/* Pipe B CRC regs */

#define _PIPE_CRC_CTL_B			0x61050

#define _PIPE_CRC_CTL_B			0x61050
@@ -1884,16 +1884,16 @@ 
#define PIPE_CRC_RES_5_IVB(pipe)	\

#define PIPE_CRC_RES_5_IVB(pipe)	\

	_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)

	_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)





#define PIPE_CRC_RES_RED_ILK(pipe) \

#define PIPE_CRC_RES_RED(pipe) \

	_PIPE_INC(pipe, _PIPE_CRC_RES_RED_A_ILK, 0x01000)

	_PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000)

#define PIPE_CRC_RES_GREEN_ILK(pipe) \

#define PIPE_CRC_RES_GREEN(pipe) \

	_PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A_ILK, 0x01000)

	_PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000)

#define PIPE_CRC_RES_BLUE_ILK(pipe) \

#define PIPE_CRC_RES_BLUE(pipe) \

	_PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A_ILK, 0x01000)

	_PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000)

#define PIPE_CRC_RES_RES1_ILK(pipe) \

#define PIPE_CRC_RES_RES1_I915(pipe) \

	_PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_ILK, 0x01000)

	_PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000)

#define PIPE_CRC_RES_RES2_ILK(pipe) \

#define PIPE_CRC_RES_RES2_G4X(pipe) \

	_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_ILK, 0x01000)

	_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)





/* Pipe A timing regs */

/* Pipe A timing regs */

#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)

#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)