Merge "ARM: dts: msm: specify I2C configuration for msmfalcon" (07d79c74) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi

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		@@ -22,11 +22,203 @@
		spi6 = &spi_6;
		spi7 = &spi_7;
		spi8 = &spi_8;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		i2c8 = &i2c_8;
		};
		};


		&soc {
		i2c_1: i2c@c175000 { /* BLSP1 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc175000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 95 0>;
		dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
		<&dma_blsp1 5 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_1_active>;
		pinctrl-1 = <&i2c_1_sleep>;
		status = "disabled";
		};

		i2c_2: i2c@c176000 { /* BLSP1 QUP2 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc176000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 96 0>;
		dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
		<&dma_blsp1 7 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_2_active>;
		pinctrl-1 = <&i2c_2_sleep>;
		status = "disabled";
		};

		i2c_3: i2c@c177000 { /* BLSP1 QUP3 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc177000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 97 0>;
		dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
		<&dma_blsp1 9 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_3_active>;
		pinctrl-1 = <&i2c_3_sleep>;
		status = "disabled";
		};

		i2c_4: i2c@c178000 { /* BLSP1 QUP4 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc178000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 98 0>;
		dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
		<&dma_blsp1 11 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_4_active>;
		pinctrl-1 = <&i2c_4_sleep>;
		status = "disabled";
		};

		i2c_5: i2c@c1b5000 { /* BLSP2 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc1b5000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 101 0>;
		dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
		<&dma_blsp2 5 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <84>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
		<&clock_gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_5_active>;
		pinctrl-1 = <&i2c_5_sleep>;
		status = "disabled";
		};

		i2c_6: i2c@c1b6000 { /* BLSP2 QUP2 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc1b6000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 102 0>;
		dmas = <&dma_blsp2 6 64 0x20000020 0x20>,
		<&dma_blsp2 7 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <84>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
		<&clock_gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_6_active>;
		pinctrl-1 = <&i2c_6_sleep>;
		status = "disabled";
		};

		i2c_7: i2c@c1b7000 { /* BLSP2 QUP3 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc1b7000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 103 0>;
		dmas = <&dma_blsp2 8 64 0x20000020 0x20>,
		<&dma_blsp2 9 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <84>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
		<&clock_gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_7_active>;
		pinctrl-1 = <&i2c_7_sleep>;
		status = "disabled";
		};

		i2c_8: i2c@c1b8000 { /* BLSP2 QUP4 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc1b8000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 104 0>;
		dmas = <&dma_blsp2 10 64 0x20000020 0x20>,
		<&dma_blsp2 11 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <84>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
		<&clock_gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_8_active>;
		pinctrl-1 = <&i2c_8_sleep>;
		status = "disabled";
		};

		spi_1: spi@c175000 { /* BLSP1 QUP1 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;

arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi

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		@@ -113,6 +113,231 @@
		};
		};

		/* I2C CONFIGURATION */
		i2c_1 {
		i2c_1_active: i2c_1_active {
		mux {
		pins = "gpio2", "gpio3";
		function = "blsp_i2c1";
		};

		config {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_1_sleep: i2c_1_sleep {
		mux {
		pins = "gpio2", "gpio3";
		function = "blsp_i2c1";
		};

		config {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_2 {
		i2c_2_active: i2c_2_active {
		mux {
		pins = "gpio6", "gpio7";
		function = "blsp_i2c2";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_2_sleep: i2c_2_sleep {
		mux {
		pins = "gpio6", "gpio7";
		function = "blsp_i2c2";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_3 {
		i2c_3_active: i2c_3_active {
		mux {
		pins = "gpio10", "gpio11";
		function = "blsp_i2c3";
		};

		config {
		pins = "gpio10", "gpio11";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_3_sleep: i2c_3_sleep {
		mux {
		pins = "gpio10", "gpio11";
		function = "blsp_i2c3";
		};

		config {
		pins = "gpio10", "gpio11";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_4 {
		i2c_4_active: i2c_4_active {
		mux {
		pins = "gpio14", "gpio15";
		function = "blsp_i2c4";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_4_sleep: i2c_4_sleep {
		mux {
		pins = "gpio14", "gpio15";
		function = "blsp_i2c4";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_5 {
		i2c_5_active: i2c_5_active {
		mux {
		pins = "gpio18", "gpio19";
		function = "blsp_i2c5";
		};

		config {
		pins = "gpio18", "gpio19";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_5_sleep: i2c_5_sleep {
		mux {
		pins = "gpio18", "gpio19";
		function = "blsp_i2c5";
		};

		config {
		pins = "gpio18", "gpio19";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_6 {
		i2c_6_active: i2c_6_active {
		mux {
		pins = "gpio22", "gpio23";
		function = "blsp_i2c6";
		};

		config {
		pins = "gpio22", "gpio23";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_6_sleep: i2c_6_sleep {
		mux {
		pins = "gpio22", "gpio23";
		function = "blsp_i2c6";
		};

		config {
		pins = "gpio22", "gpio23";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_7 {
		i2c_7_active: i2c_7_active {
		mux {
		pins = "gpio26", "gpio27";
		function = "blsp_i2c7";
		};

		config {
		pins = "gpio26", "gpio27";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_7_sleep: i2c_7_sleep {
		mux {
		pins = "gpio26", "gpio27";
		function = "blsp_i2c7";
		};

		config {
		pins = "gpio26", "gpio27";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		i2c_8 {
		i2c_8_active: i2c_8_active {
		mux {
		pins = "gpio30", "gpio31";
		function = "blsp_i2c8_a";
		};

		config {
		pins = "gpio30", "gpio31";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_8_sleep: i2c_8_sleep {
		mux {
		pins = "gpio30", "gpio31";
		function = "blsp_i2c8_a";
		};

		config {
		pins = "gpio30", "gpio31";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SPI CONFIGURATION */
		spi_1 {
		spi_1_active: spi_1_active {

arch/arm/boot/dts/qcom/msmfalcon.dtsi

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		@@ -249,6 +249,22 @@
		clock-frequency = <19200000>;
		};

		dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */
		#dma-cells = <4>;
		compatible = "qcom,sps-dma";
		reg = <0xc144000 0x1F000>;
		interrupts = <0 238 0>;
		qcom,summing-threshold = <0x10>;
		};

		dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */
		#dma-cells = <4>;
		compatible = "qcom,sps-dma";
		reg = <0xc184000 0x1F000>;
		interrupts = <0 239 0>;
		qcom,summing-threshold = <0x10>;
		};

		spmi_bus: qcom,spmi@800f000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0x800f000 0x1000>,