Loading drivers/scsi/ufs/ufshcd.c +102 −35 Original line number Diff line number Diff line Loading @@ -352,7 +352,7 @@ static inline bool ufshcd_is_valid_pm_lvl(int lvl) } static irqreturn_t ufshcd_intr(int irq, void *__hba); static void ufshcd_tmc_handler(struct ufs_hba *hba); static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); static void ufshcd_async_scan(void *data, async_cookie_t cookie); static int ufshcd_reset_and_restore(struct ufs_hba *hba); static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); Loading Loading @@ -5242,19 +5242,29 @@ ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) * ufshcd_uic_cmd_compl - handle completion of uic command * @hba: per adapter instance * @intr_status: interrupt status generated by the controller * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) { irqreturn_t retval = IRQ_NONE; if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { hba->active_uic_cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); hba->active_uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); complete(&hba->active_uic_cmd->done); retval = IRQ_HANDLED; } if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { complete(hba->uic_async_done); retval = IRQ_HANDLED; } return retval; } /** Loading Loading @@ -5399,8 +5409,12 @@ static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, /** * ufshcd_transfer_req_compl - handle SCSI and query command completion * @hba: per adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_transfer_req_compl(struct ufs_hba *hba) static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) { unsigned long completed_reqs; u32 tr_doorbell; Loading @@ -5418,7 +5432,12 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba) tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); completed_reqs = tr_doorbell ^ hba->outstanding_reqs; if (completed_reqs) { __ufshcd_transfer_req_compl(hba, completed_reqs); return IRQ_HANDLED; } else { return IRQ_NONE; } } /** Loading Loading @@ -5996,10 +6015,15 @@ static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist, /** * ufshcd_update_uic_error - check and set fatal UIC error flags. * @hba: per-adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_update_uic_error(struct ufs_hba *hba) static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) { u32 reg; irqreturn_t retval = IRQ_NONE; /* PHY layer lane error */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); Loading @@ -6026,11 +6050,13 @@ static void ufshcd_update_uic_error(struct ufs_hba *hba) } } } retval |= IRQ_HANDLED; } /* PA_INIT_ERROR is fatal and needs UIC reset */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); if (reg) if ((reg & UIC_DATA_LINK_LAYER_ERROR) && (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg); if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) { Loading @@ -6040,47 +6066,63 @@ static void ufshcd_update_uic_error(struct ufs_hba *hba) if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) hba->uic_error |= UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; } retval |= IRQ_HANDLED; } /* UIC NL/TL/DME errors needs software retry */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); if (reg) { if ((reg & UIC_NETWORK_LAYER_ERROR) && (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg); hba->uic_error |= UFSHCD_UIC_NL_ERROR; retval |= IRQ_HANDLED; } reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); if (reg) { if ((reg & UIC_TRANSPORT_LAYER_ERROR) && (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg); hba->uic_error |= UFSHCD_UIC_TL_ERROR; retval |= IRQ_HANDLED; } reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); if (reg) { if ((reg & UIC_DME_ERROR) && (reg & UIC_DME_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg); hba->uic_error |= UFSHCD_UIC_DME_ERROR; retval |= IRQ_HANDLED; } dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", __func__, hba->uic_error); return retval; } /** * ufshcd_check_errors - Check for errors that need s/w attention * @hba: per-adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_check_errors(struct ufs_hba *hba) static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba) { bool queue_eh_work = false; irqreturn_t retval = IRQ_NONE; if (hba->errors & INT_FATAL_ERRORS || hba->ce_error) queue_eh_work = true; if (hba->errors & UIC_ERROR) { hba->uic_error = 0; ufshcd_update_uic_error(hba); retval = ufshcd_update_uic_error(hba); if (hba->uic_error) queue_eh_work = true; } Loading @@ -6105,6 +6147,7 @@ static void ufshcd_check_errors(struct ufs_hba *hba) hba->ufshcd_state = UFSHCD_STATE_ERROR; schedule_work(&hba->eh_work); } retval |= IRQ_HANDLED; } /* * if (!queue_eh_work) - Loading @@ -6112,28 +6155,44 @@ static void ufshcd_check_errors(struct ufs_hba *hba) * itself without s/w intervention or errors that will be * handled by the SCSI core layer. */ return retval; } /** * ufshcd_tmc_handler - handle task management function completion * @hba: per adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_tmc_handler(struct ufs_hba *hba) static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) { u32 tm_doorbell; tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks; if (hba->tm_condition) { wake_up(&hba->tm_wq); return IRQ_HANDLED; } else { return IRQ_NONE; } } /** * ufshcd_sl_intr - Interrupt service routine * @hba: per adapter instance * @intr_status: contains interrupts generated by the controller * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) { irqreturn_t retval = IRQ_NONE; ufsdbg_error_inject_dispatcher(hba, ERR_INJECT_INTR, intr_status, &intr_status); Loading @@ -6141,16 +6200,18 @@ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) hba->errors = UFSHCD_ERROR_MASK & intr_status; if (hba->errors || hba->ce_error) ufshcd_check_errors(hba); retval |= ufshcd_check_errors(hba); if (intr_status & UFSHCD_UIC_MASK) ufshcd_uic_cmd_compl(hba, intr_status); retval |= ufshcd_uic_cmd_compl(hba, intr_status); if (intr_status & UTP_TASK_REQ_COMPL) ufshcd_tmc_handler(hba); retval |= ufshcd_tmc_handler(hba); if (intr_status & UTP_TRANSFER_REQ_COMPL) ufshcd_transfer_req_compl(hba); retval |= ufshcd_transfer_req_compl(hba); return retval; } /** Loading @@ -6158,7 +6219,8 @@ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) * @irq: irq number * @__hba: pointer to adapter instance * * Returns IRQ_HANDLED - If interrupt is valid * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static irqreturn_t ufshcd_intr(int irq, void *__hba) Loading @@ -6182,14 +6244,19 @@ static irqreturn_t ufshcd_intr(int irq, void *__hba) intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); if (intr_status) ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); if (enabled_intr_status) { ufshcd_sl_intr(hba, enabled_intr_status); retval = IRQ_HANDLED; } if (enabled_intr_status) retval |= ufshcd_sl_intr(hba, enabled_intr_status); intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); } while (intr_status && --retries); if (retval == IRQ_NONE) { dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n", __func__, intr_status); ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE); } spin_unlock(hba->host->host_lock); return retval; } Loading Loading
drivers/scsi/ufs/ufshcd.c +102 −35 Original line number Diff line number Diff line Loading @@ -352,7 +352,7 @@ static inline bool ufshcd_is_valid_pm_lvl(int lvl) } static irqreturn_t ufshcd_intr(int irq, void *__hba); static void ufshcd_tmc_handler(struct ufs_hba *hba); static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); static void ufshcd_async_scan(void *data, async_cookie_t cookie); static int ufshcd_reset_and_restore(struct ufs_hba *hba); static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); Loading Loading @@ -5242,19 +5242,29 @@ ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) * ufshcd_uic_cmd_compl - handle completion of uic command * @hba: per adapter instance * @intr_status: interrupt status generated by the controller * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) { irqreturn_t retval = IRQ_NONE; if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { hba->active_uic_cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); hba->active_uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); complete(&hba->active_uic_cmd->done); retval = IRQ_HANDLED; } if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { complete(hba->uic_async_done); retval = IRQ_HANDLED; } return retval; } /** Loading Loading @@ -5399,8 +5409,12 @@ static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, /** * ufshcd_transfer_req_compl - handle SCSI and query command completion * @hba: per adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_transfer_req_compl(struct ufs_hba *hba) static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) { unsigned long completed_reqs; u32 tr_doorbell; Loading @@ -5418,7 +5432,12 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba) tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); completed_reqs = tr_doorbell ^ hba->outstanding_reqs; if (completed_reqs) { __ufshcd_transfer_req_compl(hba, completed_reqs); return IRQ_HANDLED; } else { return IRQ_NONE; } } /** Loading Loading @@ -5996,10 +6015,15 @@ static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist, /** * ufshcd_update_uic_error - check and set fatal UIC error flags. * @hba: per-adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_update_uic_error(struct ufs_hba *hba) static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) { u32 reg; irqreturn_t retval = IRQ_NONE; /* PHY layer lane error */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); Loading @@ -6026,11 +6050,13 @@ static void ufshcd_update_uic_error(struct ufs_hba *hba) } } } retval |= IRQ_HANDLED; } /* PA_INIT_ERROR is fatal and needs UIC reset */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); if (reg) if ((reg & UIC_DATA_LINK_LAYER_ERROR) && (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg); if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) { Loading @@ -6040,47 +6066,63 @@ static void ufshcd_update_uic_error(struct ufs_hba *hba) if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) hba->uic_error |= UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; } retval |= IRQ_HANDLED; } /* UIC NL/TL/DME errors needs software retry */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); if (reg) { if ((reg & UIC_NETWORK_LAYER_ERROR) && (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg); hba->uic_error |= UFSHCD_UIC_NL_ERROR; retval |= IRQ_HANDLED; } reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); if (reg) { if ((reg & UIC_TRANSPORT_LAYER_ERROR) && (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg); hba->uic_error |= UFSHCD_UIC_TL_ERROR; retval |= IRQ_HANDLED; } reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); if (reg) { if ((reg & UIC_DME_ERROR) && (reg & UIC_DME_ERROR_CODE_MASK)) { ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg); hba->uic_error |= UFSHCD_UIC_DME_ERROR; retval |= IRQ_HANDLED; } dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", __func__, hba->uic_error); return retval; } /** * ufshcd_check_errors - Check for errors that need s/w attention * @hba: per-adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_check_errors(struct ufs_hba *hba) static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba) { bool queue_eh_work = false; irqreturn_t retval = IRQ_NONE; if (hba->errors & INT_FATAL_ERRORS || hba->ce_error) queue_eh_work = true; if (hba->errors & UIC_ERROR) { hba->uic_error = 0; ufshcd_update_uic_error(hba); retval = ufshcd_update_uic_error(hba); if (hba->uic_error) queue_eh_work = true; } Loading @@ -6105,6 +6147,7 @@ static void ufshcd_check_errors(struct ufs_hba *hba) hba->ufshcd_state = UFSHCD_STATE_ERROR; schedule_work(&hba->eh_work); } retval |= IRQ_HANDLED; } /* * if (!queue_eh_work) - Loading @@ -6112,28 +6155,44 @@ static void ufshcd_check_errors(struct ufs_hba *hba) * itself without s/w intervention or errors that will be * handled by the SCSI core layer. */ return retval; } /** * ufshcd_tmc_handler - handle task management function completion * @hba: per adapter instance * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_tmc_handler(struct ufs_hba *hba) static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) { u32 tm_doorbell; tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks; if (hba->tm_condition) { wake_up(&hba->tm_wq); return IRQ_HANDLED; } else { return IRQ_NONE; } } /** * ufshcd_sl_intr - Interrupt service routine * @hba: per adapter instance * @intr_status: contains interrupts generated by the controller * * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) { irqreturn_t retval = IRQ_NONE; ufsdbg_error_inject_dispatcher(hba, ERR_INJECT_INTR, intr_status, &intr_status); Loading @@ -6141,16 +6200,18 @@ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) hba->errors = UFSHCD_ERROR_MASK & intr_status; if (hba->errors || hba->ce_error) ufshcd_check_errors(hba); retval |= ufshcd_check_errors(hba); if (intr_status & UFSHCD_UIC_MASK) ufshcd_uic_cmd_compl(hba, intr_status); retval |= ufshcd_uic_cmd_compl(hba, intr_status); if (intr_status & UTP_TASK_REQ_COMPL) ufshcd_tmc_handler(hba); retval |= ufshcd_tmc_handler(hba); if (intr_status & UTP_TRANSFER_REQ_COMPL) ufshcd_transfer_req_compl(hba); retval |= ufshcd_transfer_req_compl(hba); return retval; } /** Loading @@ -6158,7 +6219,8 @@ static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) * @irq: irq number * @__hba: pointer to adapter instance * * Returns IRQ_HANDLED - If interrupt is valid * Returns * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static irqreturn_t ufshcd_intr(int irq, void *__hba) Loading @@ -6182,14 +6244,19 @@ static irqreturn_t ufshcd_intr(int irq, void *__hba) intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); if (intr_status) ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); if (enabled_intr_status) { ufshcd_sl_intr(hba, enabled_intr_status); retval = IRQ_HANDLED; } if (enabled_intr_status) retval |= ufshcd_sl_intr(hba, enabled_intr_status); intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); } while (intr_status && --retries); if (retval == IRQ_NONE) { dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n", __func__, intr_status); ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE); } spin_unlock(hba->host->host_lock); return retval; } Loading