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Commit 0671bdd7 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls 



It's handled via external clock. It should already be protected
by the external ss flag, but add an explicit check just in case.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 64199870

drivers/gpu/drm/radeon/atombios_crtc.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -474,7 +474,7 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev, 
			return;

			return;

		}

		}

		args.v3.ucEnable = enable;

		args.v3.ucEnable = enable;

		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))

		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))

			args.v3.ucEnable = ATOM_DISABLE;

			args.v3.ucEnable = ATOM_DISABLE;

	} else if (ASIC_IS_DCE4(rdev)) {

	} else if (ASIC_IS_DCE4(rdev)) {

		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);