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Commit 06185c07 authored by Seungwhan Youn's avatar Seungwhan Youn Committed by Kukjin Kim
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ARM: S5P6442: Add DMA operation clock 



This patch adds DMA operation clock which is disabled as default.

Signed-off-by: default avatarSeungwhan Youn <sw.youn@samsung.com>
Acked-by: default avatarJassi Brar <jassi.brar@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 8e0e9e29

arch/arm/mach-s5p6442/clock.c

+28 −0
Original line number Diff line number Diff line
@@ -192,6 +192,11 @@ static struct clk clk_pclkd1 = { 
	.parent		= &clk_hclkd1,

};



int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);

}



int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
@@ -335,6 +340,16 @@ void __init_or_cpufreq s5p6442_setup_clocks(void) 
	clk_pclkd1.rate = pclkd1;

}



static struct clk init_clocks_disable[] = {

	{

		.name		= "pdma",

		.id		= -1,

		.parent		= &clk_pclkd1,

		.enable		= s5p6442_clk_ip0_ctrl,

		.ctrlbit	= (1 << 3),

	},

};



static struct clk init_clocks[] = {

	{

		.name		= "systimer",
@@ -393,10 +408,23 @@ static struct clk *clks[] __initdata = { 


void __init s5p6442_register_clocks(void)

{

	struct clk *clkptr;

	int i, ret;



	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));



	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));



	clkptr = init_clocks_disable;

	for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {

		ret = s3c24xx_register_clock(clkptr);

		if (ret < 0) {

			printk(KERN_ERR "Fail to register clock %s (%d)\n",

					clkptr->name, ret);

		} else

			(clkptr->enable)(clkptr, 0);

	}



	s3c_pwmclk_init();

}

arch/arm/mach-s5p6442/include/mach/regs-clock.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#define S5P_CLK_DIV5		S5P_CLKREG(0x314)

#define S5P_CLK_DIV6		S5P_CLKREG(0x318)



#define S5P_CLKGATE_IP0		S5P_CLKREG(0x460)

#define S5P_CLKGATE_IP3		S5P_CLKREG(0x46C)



/* CLK_OUT */