Loading arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -203,8 +203,7 @@ < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; qcom,gfxfreq-mx-speedbin0 = < 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, Loading @@ -213,8 +212,7 @@ < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; &mdss_mdp { Loading drivers/clk/msm/clock-gpu-cobalt.c +1 −2 Original line number Diff line number Diff line Loading @@ -173,7 +173,6 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src_v2[] = { F_SLEW( 515000000, 1030000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 596000000, 1192000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 670000000, 1340000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 710000000, 1420000000, gpu_pll0_pll_out_even, 1, 0, 0), F_END }; Loading Loading @@ -612,7 +611,7 @@ static void msm_gfxcc_hamster_fixup(void) static void msm_gfxcc_cobalt_v2_fixup(void) { gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500; gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1340000500; gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2; } Loading Loading
arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -203,8 +203,7 @@ < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; qcom,gfxfreq-mx-speedbin0 = < 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, Loading @@ -213,8 +212,7 @@ < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; &mdss_mdp { Loading
drivers/clk/msm/clock-gpu-cobalt.c +1 −2 Original line number Diff line number Diff line Loading @@ -173,7 +173,6 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src_v2[] = { F_SLEW( 515000000, 1030000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 596000000, 1192000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 670000000, 1340000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 710000000, 1420000000, gpu_pll0_pll_out_even, 1, 0, 0), F_END }; Loading Loading @@ -612,7 +611,7 @@ static void msm_gfxcc_hamster_fixup(void) static void msm_gfxcc_cobalt_v2_fixup(void) { gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500; gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1340000500; gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2; } Loading