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Commit 03f896a1 authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Daniel Vetter
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drm/i915: add definitions for DDI_BUF_CTL registers 



There is one instance of those registers for each DDI port.

v2: access registers via the DDI_BUF_CTL() macro

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e411b2c1

drivers/gpu/drm/i915/i915_reg.h

+23 −0
Original line number Diff line number Diff line
@@ -4086,4 +4086,27 @@ 
					DP_TP_STATUS_B)

#define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)



/* DDI Buffer Control */

#define DDI_BUF_CTL_A				0x64000

#define DDI_BUF_CTL_B				0x64100

#define DDI_BUF_CTL(port) _PORT(port, \

					DDI_BUF_CTL_A, \

					DDI_BUF_CTL_B)

#define  DDI_BUF_CTL_ENABLE				(1<<31)

#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */

#define  DDI_BUF_EMP_400MV_3_5DB_HSW	(1<<24)   /* Sel1 */

#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */

#define  DDI_BUF_EMP_400MV_9_5DB_HSW	(3<<24)   /* Sel3 */

#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */

#define  DDI_BUF_EMP_600MV_3_5DB_HSW	(5<<24)   /* Sel5 */

#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */

#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */

#define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */

#define  DDI_BUF_EMP_MASK				(0xf<<24)

#define  DDI_BUF_IS_IDLE				(1<<7)

#define  DDI_PORT_WIDTH_X1				(0<<1)

#define  DDI_PORT_WIDTH_X2				(1<<1)

#define  DDI_PORT_WIDTH_X4				(3<<1)

#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)



#endif /* _I915_REG_H_ */