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Commit 03ac4137 authored by Marc Zyngier's avatar Marc Zyngier Committed by Gerrit - the friendly Code Review server
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arm64: Move BP hardening to check_and_switch_context 



We call arm64_apply_bp_hardening() from post_ttbr_update_workaround,
which has the unexpected consequence of being triggered on every
exception return to userspace when ARM64_SW_TTBR0_PAN is selected,
even if no context switch actually occured.

This is a bit suboptimal, and it would be more logical to only
invalidate the branch predictor when we actually switch to
a different mm.

In order to solve this, move the call to arm64_apply_bp_hardening()
into check_and_switch_context(), where we're guaranteed to pick
a different mm context.

Change-Id: I28f2fb09b77544e5ead095e9dad1ad64b2b3ae36
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Git-commit: a8e4c0a919ae310944ed2c9ace11cf3ccd8a609b
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent 21393ff3

arch/arm64/mm/context.c

+3 −2
Original line number Diff line number Diff line
@@ -191,6 +191,9 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) 
	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);



switch_mm_fastpath:



	arm64_apply_bp_hardening();



	/*

	 * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when

	 * emulating PAN.
@@ -206,8 +209,6 @@ asmlinkage void post_ttbr_update_workaround(void) 
			"ic iallu; dsb nsh; isb",

			ARM64_WORKAROUND_CAVIUM_27456,

			CONFIG_CAVIUM_ERRATUM_27456));



	arm64_apply_bp_hardening();

}



static int asids_init(void)