Loading drivers/video/fbdev/msm/mdss_dp.h +0 −9 Original line number Diff line number Diff line Loading @@ -106,15 +106,6 @@ #define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2) struct edp_cmd { char read; /* 1 == read, 0 == write */ char i2c; /* 1 == i2c cmd, 0 == native cmd */ u32 addr; /* 20 bits */ char *datap; int len; /* len to be tx OR len to be rx for read */ char next; /* next command */ }; struct edp_buf { char *start; /* buffer start addr */ char *end; /* buffer end addr */ Loading drivers/video/fbdev/msm/mdss_dp_aux.c +13 −0 Original line number Diff line number Diff line Loading @@ -228,6 +228,11 @@ static int dp_aux_write_cmds(struct mdss_dp_drv_pdata *ep, return ret; } int dp_aux_write(void *ep, struct edp_cmd *cmd) { return dp_aux_write_cmds(ep, cmd); } static int dp_aux_read_cmds(struct mdss_dp_drv_pdata *ep, struct edp_cmd *cmds) { Loading Loading @@ -275,12 +280,20 @@ static int dp_aux_read_cmds(struct mdss_dp_drv_pdata *ep, else ret = ep->aux_error_num; if (cmds->out_buf) memcpy(cmds->out_buf, rp->data, cmds->len); ep->aux_cmd_busy = 0; mutex_unlock(&ep->aux_mutex); return ret; } int dp_aux_read(void *ep, struct edp_cmd *cmds) { return dp_aux_read_cmds(ep, cmds); } void dp_aux_native_handler(struct mdss_dp_drv_pdata *ep, u32 isr) { Loading drivers/video/fbdev/msm/mdss_dp_util.h +38 −0 Original line number Diff line number Diff line Loading @@ -88,6 +88,32 @@ #define TCSR_USB3_DP_PHYMODE 0x48 #define EDID_START_ADDRESS 0x50 /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL (0x0A0) #define DP_HDCP_STATUS (0x0A4) #define DP_HDCP_SW_UPPER_AKSV (0x298) #define DP_HDCP_SW_LOWER_AKSV (0x29C) #define DP_HDCP_ENTROPY_CTRL0 (0x750) #define DP_HDCP_ENTROPY_CTRL1 (0x75C) #define DP_HDCP_SHA_STATUS (0x0C8) #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) #define DP_HDCP_RCVPORT_DATA3 (0x2A4) #define DP_HDCP_RCVPORT_DATA4 (0x2A8) #define DP_HDCP_RCVPORT_DATA5 (0x0C0) #define DP_HDCP_RCVPORT_DATA6 (0x0C4) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) #define DP_INTERRUPT_STATUS_2 (0x024) struct lane_mapping { char lane0; char lane1; Loading @@ -95,6 +121,18 @@ struct lane_mapping { char lane3; }; struct edp_cmd { char read; /* 1 == read, 0 == write */ char i2c; /* 1 == i2c cmd, 0 == native cmd */ u32 addr; /* 20 bits */ char *datap; char *out_buf; int len; /* len to be tx OR len to be rx for read */ char next; /* next command */ }; int dp_aux_read(void *ep, struct edp_cmd *cmds); int dp_aux_write(void *ep, struct edp_cmd *cmd); void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data); u32 mdss_dp_get_ctrl_hw_version(struct dss_io_data *ctrl_io); u32 mdss_dp_get_phy_hw_version(struct dss_io_data *phy_io); Loading drivers/video/fbdev/msm/mdss_hdmi_hdcp.c +581 −425 File changed.Preview size limit exceeded, changes collapsed. Show changes drivers/video/fbdev/msm/mdss_hdmi_hdcp.h +9 −1 Original line number Diff line number Diff line /* Copyright (c) 2012, 2014-2015 The Linux Foundation. All rights reserved. /* Copyright (c) 2012, 2014-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -17,6 +17,11 @@ #include <video/msm_hdmi_modes.h> #include <soc/qcom/scm.h> enum hdcp_client_id { HDCP_CLIENT_HDMI, HDCP_CLIENT_DP, }; enum hdmi_hdcp_state { HDCP_STATE_INACTIVE, HDCP_STATE_AUTHENTICATING, Loading @@ -37,10 +42,13 @@ struct hdmi_hdcp_init_data { void *cb_data; void (*notify_status)(void *cb_data, enum hdmi_hdcp_state status); struct hdmi_tx_ddc_ctrl *ddc_ctrl; void *dp_data; u32 phy_addr; u32 hdmi_tx_ver; struct msm_hdmi_mode_timing_info *timing; bool tethered; bool sec_access; enum hdcp_client_id client_id; }; struct hdmi_hdcp_ops { Loading Loading
drivers/video/fbdev/msm/mdss_dp.h +0 −9 Original line number Diff line number Diff line Loading @@ -106,15 +106,6 @@ #define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2) struct edp_cmd { char read; /* 1 == read, 0 == write */ char i2c; /* 1 == i2c cmd, 0 == native cmd */ u32 addr; /* 20 bits */ char *datap; int len; /* len to be tx OR len to be rx for read */ char next; /* next command */ }; struct edp_buf { char *start; /* buffer start addr */ char *end; /* buffer end addr */ Loading
drivers/video/fbdev/msm/mdss_dp_aux.c +13 −0 Original line number Diff line number Diff line Loading @@ -228,6 +228,11 @@ static int dp_aux_write_cmds(struct mdss_dp_drv_pdata *ep, return ret; } int dp_aux_write(void *ep, struct edp_cmd *cmd) { return dp_aux_write_cmds(ep, cmd); } static int dp_aux_read_cmds(struct mdss_dp_drv_pdata *ep, struct edp_cmd *cmds) { Loading Loading @@ -275,12 +280,20 @@ static int dp_aux_read_cmds(struct mdss_dp_drv_pdata *ep, else ret = ep->aux_error_num; if (cmds->out_buf) memcpy(cmds->out_buf, rp->data, cmds->len); ep->aux_cmd_busy = 0; mutex_unlock(&ep->aux_mutex); return ret; } int dp_aux_read(void *ep, struct edp_cmd *cmds) { return dp_aux_read_cmds(ep, cmds); } void dp_aux_native_handler(struct mdss_dp_drv_pdata *ep, u32 isr) { Loading
drivers/video/fbdev/msm/mdss_dp_util.h +38 −0 Original line number Diff line number Diff line Loading @@ -88,6 +88,32 @@ #define TCSR_USB3_DP_PHYMODE 0x48 #define EDID_START_ADDRESS 0x50 /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL (0x0A0) #define DP_HDCP_STATUS (0x0A4) #define DP_HDCP_SW_UPPER_AKSV (0x298) #define DP_HDCP_SW_LOWER_AKSV (0x29C) #define DP_HDCP_ENTROPY_CTRL0 (0x750) #define DP_HDCP_ENTROPY_CTRL1 (0x75C) #define DP_HDCP_SHA_STATUS (0x0C8) #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) #define DP_HDCP_RCVPORT_DATA3 (0x2A4) #define DP_HDCP_RCVPORT_DATA4 (0x2A8) #define DP_HDCP_RCVPORT_DATA5 (0x0C0) #define DP_HDCP_RCVPORT_DATA6 (0x0C4) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) #define DP_INTERRUPT_STATUS_2 (0x024) struct lane_mapping { char lane0; char lane1; Loading @@ -95,6 +121,18 @@ struct lane_mapping { char lane3; }; struct edp_cmd { char read; /* 1 == read, 0 == write */ char i2c; /* 1 == i2c cmd, 0 == native cmd */ u32 addr; /* 20 bits */ char *datap; char *out_buf; int len; /* len to be tx OR len to be rx for read */ char next; /* next command */ }; int dp_aux_read(void *ep, struct edp_cmd *cmds); int dp_aux_write(void *ep, struct edp_cmd *cmd); void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data); u32 mdss_dp_get_ctrl_hw_version(struct dss_io_data *ctrl_io); u32 mdss_dp_get_phy_hw_version(struct dss_io_data *phy_io); Loading
drivers/video/fbdev/msm/mdss_hdmi_hdcp.c +581 −425 File changed.Preview size limit exceeded, changes collapsed. Show changes
drivers/video/fbdev/msm/mdss_hdmi_hdcp.h +9 −1 Original line number Diff line number Diff line /* Copyright (c) 2012, 2014-2015 The Linux Foundation. All rights reserved. /* Copyright (c) 2012, 2014-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -17,6 +17,11 @@ #include <video/msm_hdmi_modes.h> #include <soc/qcom/scm.h> enum hdcp_client_id { HDCP_CLIENT_HDMI, HDCP_CLIENT_DP, }; enum hdmi_hdcp_state { HDCP_STATE_INACTIVE, HDCP_STATE_AUTHENTICATING, Loading @@ -37,10 +42,13 @@ struct hdmi_hdcp_init_data { void *cb_data; void (*notify_status)(void *cb_data, enum hdmi_hdcp_state status); struct hdmi_tx_ddc_ctrl *ddc_ctrl; void *dp_data; u32 phy_addr; u32 hdmi_tx_ver; struct msm_hdmi_mode_timing_info *timing; bool tethered; bool sec_access; enum hdcp_client_id client_id; }; struct hdmi_hdcp_ops { Loading