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Commit 035a61c3 authored by Tomeu Vizoso's avatar Tomeu Vizoso Committed by Michael Turquette
Browse files

clk: Make clk API return per-user struct clk instances 



Moves clock state to struct clk_core, but takes care to change as little API as
possible.

struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.

The struct clk that clk_get_parent() returns isn't owned by the caller, but by
the clock implementation, so the former shouldn't call clk_put() on it.

Because some boards in mach-omap2 still register clocks statically, their clock
registration had to be updated to take into account that the clock information
is stored in struct clk_core now.

Signed-off-by: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Tested-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: adapted clk_has_parent to struct clk_core
                        applied OMAP3+ DPLL fix from Tero & Tony]
parent af0f349b

arch/arm/mach-omap2/cclock3xxx_data.c

+73 −38
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0, 
	       OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,

	       OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);



DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,

DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck_core, 0x0,

		   OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,

		   OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
@@ -132,7 +132,7 @@ static struct clk_hw_omap dpll3_ck_hw = { 


DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);



DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck_core, 0x0,

		   OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),

		   OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,

		   OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
@@ -149,12 +149,12 @@ static const struct clk_ops core_ck_ops = {}; 
DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);

DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);



DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,

DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck_core, 0x0,

		   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),

		   OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);



DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,

DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick_core, 0x0,

		   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),

		   OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -275,9 +275,9 @@ static struct clk_hw_omap dpll1_ck_hw = { 


DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);



DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);

DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck_core, 0x0, 2, 1);



DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck_core, 0x0,

		   OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),

		   OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,

		   OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
@@ -292,7 +292,7 @@ static const char *mpu_ck_parent_names[] = { 
DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");

DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);



DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,

DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck_core, 0x0,

		   OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),

		   OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,

		   0x0, NULL);
@@ -424,7 +424,7 @@ static const struct clk_div_table dpll4_mx_ck_div_table[] = { 
	{ .div = 0 },

};



DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),

		   OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -466,7 +466,7 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { 
DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,

			dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);



static struct clk dpll4_m5x2_ck_3630 = {

static struct clk_core dpll4_m5x2_ck_3630_core = {

	.name		= "dpll4_m5x2_ck",

	.hw		= &dpll4_m5x2_ck_hw.hw,

	.parent_names	= dpll4_m5x2_ck_parent_names,
@@ -475,6 +475,10 @@ static struct clk dpll4_m5x2_ck_3630 = { 
	.flags		= CLK_SET_RATE_PARENT,

};



static struct clk dpll4_m5x2_ck_3630 = {

	.core = &dpll4_m5x2_ck_3630_core,

};



static struct clk cam_mclk;



static const char *cam_mclk_parent_names[] = {
@@ -490,7 +494,7 @@ static struct clk_hw_omap cam_mclk_hw = { 
	.clkdm_name	= "cam_clkdm",

};



static struct clk cam_mclk = {

static struct clk_core cam_mclk_core = {

	.name		= "cam_mclk",

	.hw		= &cam_mclk_hw.hw,

	.parent_names	= cam_mclk_parent_names,
@@ -499,6 +503,10 @@ static struct clk cam_mclk = { 
	.flags		= CLK_SET_RATE_PARENT,

};



static struct clk cam_mclk = {

	.core = &cam_mclk_core,

};



static const struct clksel_rate clkout2_src_core_rates[] = {

	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },

	{ .div = 0 }
@@ -514,7 +522,7 @@ static const struct clksel_rate clkout2_src_96m_rates[] = { 
	{ .div = 0 }

};



DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck_core, 0x0,

		   OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),

		   OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -538,7 +546,7 @@ static struct clk_hw_omap dpll4_m2x2_ck_hw = { 


DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);



static struct clk dpll4_m2x2_ck_3630 = {

static struct clk_core dpll4_m2x2_ck_3630_core = {

	.name		= "dpll4_m2x2_ck",

	.hw		= &dpll4_m2x2_ck_hw.hw,

	.parent_names	= dpll4_m2x2_ck_parent_names,
@@ -546,6 +554,10 @@ static struct clk dpll4_m2x2_ck_3630 = { 
	.ops		= &dpll4_m5x2_ck_3630_ops,

};



static struct clk dpll4_m2x2_ck_3630 = {

	.core = &dpll4_m2x2_ck_3630_core,

};



static struct clk omap_96m_alwon_fck;



static const char *omap_96m_alwon_fck_parent_names[] = {
@@ -570,7 +582,7 @@ static const struct clksel_rate clkout2_src_54m_rates[] = { 
	{ .div = 0 }

};



DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,

DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),

		   OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,

		   0, dpll4_mx_ck_div_table, NULL);
@@ -594,7 +606,7 @@ static struct clk_hw_omap dpll4_m3x2_ck_hw = { 


DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);



static struct clk dpll4_m3x2_ck_3630 = {

static struct clk_core dpll4_m3x2_ck_3630_core = {

	.name		= "dpll4_m3x2_ck",

	.hw		= &dpll4_m3x2_ck_hw.hw,

	.parent_names	= dpll4_m3x2_ck_parent_names,
@@ -602,6 +614,10 @@ static struct clk dpll4_m3x2_ck_3630 = { 
	.ops		= &dpll4_m5x2_ck_3630_ops,

};



static struct clk dpll4_m3x2_ck_3630 = {

	.core = &dpll4_m3x2_ck_3630_core,

};



static const char *omap_54m_fck_parent_names[] = {

	"dpll4_m3x2_ck", "sys_altclk",

};
@@ -677,7 +693,8 @@ static struct clk_hw_omap omap_48m_fck_hw = { 


DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);



DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);

DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck_core, 0x0,

			1, 4);



static struct clk core_12m_fck;
@@ -723,7 +740,8 @@ static const char *core_l3_ick_parent_names[] = { 
DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");

DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);



DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);

DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck_core, 0x0,

			2, 1);



static struct clk corex2_fck;
@@ -809,7 +827,7 @@ static struct clk_hw_omap des2_ick_hw = { 


DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);



DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck_core, 0x0,

		   OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),

		   OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -852,18 +870,18 @@ static struct clk_hw_omap dpll2_ck_hw = { 


DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);



DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),

		   OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);



DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),

		   OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,

		   OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);



DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

		   OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -887,7 +905,7 @@ static struct clk_hw_omap dpll3_m3x2_ck_hw = { 


DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);



static struct clk dpll3_m3x2_ck_3630 = {

static struct clk_core dpll3_m3x2_ck_3630_core = {

	.name		= "dpll3_m3x2_ck",

	.hw		= &dpll3_m3x2_ck_hw.hw,

	.parent_names	= dpll3_m3x2_ck_parent_names,
@@ -895,9 +913,13 @@ static struct clk dpll3_m3x2_ck_3630 = { 
	.ops		= &dpll4_m5x2_ck_3630_ops,

};



DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);

static struct clk dpll3_m3x2_ck_3630 = {

	.core = &dpll3_m3x2_ck_3630_core,

};



DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck_core, 0x0, 2, 1);



DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,

DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),

		   OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,

		   0, dpll4_mx_ck_div_table, NULL);
@@ -922,7 +944,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { 
DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,

		dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);



static struct clk dpll4_m4x2_ck_3630 = {

static struct clk_core dpll4_m4x2_ck_3630_core = {

	.name		= "dpll4_m4x2_ck",

	.hw		= &dpll4_m4x2_ck_hw.hw,

	.parent_names	= dpll4_m4x2_ck_parent_names,
@@ -931,7 +953,11 @@ static struct clk dpll4_m4x2_ck_3630 = { 
	.flags		= CLK_SET_RATE_PARENT,

};



DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,

static struct clk dpll4_m4x2_ck_3630 = {

	.core = &dpll4_m4x2_ck_3630_core,

};



DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

		   OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -955,7 +981,7 @@ static struct clk_hw_omap dpll4_m6x2_ck_hw = { 


DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);



static struct clk dpll4_m6x2_ck_3630 = {

static struct clk_core dpll4_m6x2_ck_3630_core = {

	.name		= "dpll4_m6x2_ck",

	.hw		= &dpll4_m6x2_ck_hw.hw,

	.parent_names	= dpll4_m6x2_ck_parent_names,
@@ -963,7 +989,11 @@ static struct clk dpll4_m6x2_ck_3630 = { 
	.ops		= &dpll4_m5x2_ck_3630_ops,

};



DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);

static struct clk dpll4_m6x2_ck_3630 = {

	.core = &dpll4_m6x2_ck_3630_core,

};



DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck_core, 0x0, 2, 1);



static struct dpll_data dpll5_dd = {

	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
@@ -1000,7 +1030,7 @@ static struct clk_hw_omap dpll5_ck_hw = { 


DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);



DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,

DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck_core, 0x0,

		   OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),

		   OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -1247,7 +1277,7 @@ static struct clk_hw_omap emu_src_ck_hw = { 


DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);



DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,

DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

		   OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -1298,7 +1328,7 @@ static struct clk_hw_omap gfx_l3_ck_hw = { 


DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);



DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,

DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick_core, 0x0,

		   OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),

		   OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -2498,7 +2528,7 @@ static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = { 
	.clksel_mask	= OMAP3630_CLKSEL_96M_MASK,

};



static struct clk omap_96m_alwon_fck_3630 = {

static struct clk_core omap_96m_alwon_fck_3630_core = {

	.name	= "omap_96m_alwon_fck",

	.hw	= &omap_96m_alwon_fck_3630_hw.hw,

	.parent_names	= omap_96m_alwon_fck_3630_parent_names,
@@ -2506,6 +2536,10 @@ static struct clk omap_96m_alwon_fck_3630 = { 
	.ops	= &omap_96m_alwon_fck_3630_ops,

};



static struct clk omap_96m_alwon_fck_3630 = {

	.core = &omap_96m_alwon_fck_3630_core,

};



static struct clk omapctrl_ick;



static struct clk_hw_omap omapctrl_ick_hw = {
@@ -2521,12 +2555,12 @@ static struct clk_hw_omap omapctrl_ick_hw = { 


DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);



DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,

DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

		   OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);



DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,

DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck_core, 0x0,

		   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

		   OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -2558,7 +2592,7 @@ static struct clk_hw_omap pka_ick_hw = { 


DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);



DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,

DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick_core, 0x0,

		   OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),

		   OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,

		   CLK_DIVIDER_ONE_BASED, NULL);
@@ -2819,10 +2853,10 @@ DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm", 
			 ssi_ssr_fck_3430es1_ops);



DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",

			&ssi_ssr_fck_3430es1, 0x0, 1, 2);

			&ssi_ssr_fck_3430es1_core, 0x0, 1, 2);



DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",

			&ssi_ssr_fck_3430es2, 0x0, 1, 2);

			&ssi_ssr_fck_3430es2_core, 0x0, 1, 2);



static struct clk sys_clkout1;
@@ -2840,7 +2874,7 @@ static struct clk_hw_omap sys_clkout1_hw = { 


DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);



DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,

DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck_core, 0x0,

		   OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,

		   OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
@@ -2849,7 +2883,8 @@ DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0, 
	       OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,

	       0x0, NULL);



DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,

DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck_core,

		   0x0,

		   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

		   OMAP3430_CLKSEL_TRACECLK_SHIFT,

		   OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);

arch/arm/mach-omap2/clock.h

+9 −2
Original line number Diff line number Diff line
@@ -40,23 +40,29 @@ struct omap_clk { 
struct clockdomain;



#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\

	static struct clk _name = {				\

	static struct clk_core _name##_core = {			\

		.name = #_name,					\

		.hw = &_name##_hw.hw,				\

		.parent_names = _parent_array_name,		\

		.num_parents = ARRAY_SIZE(_parent_array_name),	\

		.ops = &_clkops_name,				\

	};							\

	static struct clk _name = {				\

		.core = &_name##_core,				\

	};



#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name,	\

				_clkops_name, _flags)		\

	static struct clk _name = {				\

	static struct clk_core _name##_core = {			\

		.name = #_name,					\

		.hw = &_name##_hw.hw,				\

		.parent_names = _parent_array_name,		\

		.num_parents = ARRAY_SIZE(_parent_array_name),	\

		.ops = &_clkops_name,				\

		.flags = _flags,				\

	};							\

	static struct clk _name = {				\

		.core = &_name##_core,				\

	};



#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name)		\
@@ -248,6 +254,7 @@ extern const struct clksel_rate gpt_32k_rates[]; 
extern const struct clksel_rate gpt_sys_rates[];

extern const struct clksel_rate gfx_l3_rates[];

extern const struct clksel_rate dsp_ick_rates[];

extern struct clk_core dummy_ck_core;

extern struct clk dummy_ck;



extern const struct clk_hw_omap_ops clkhwops_iclk_wait;

arch/arm/mach-omap2/clock_common_data.c

+4 −1
Original line number Diff line number Diff line
@@ -119,8 +119,11 @@ const struct clksel_rate div31_1to31_rates[] = { 


static struct clk_ops dummy_ck_ops = {};



struct clk dummy_ck = {

struct clk_core dummy_ck_core = {

	.name = "dummy_clk",

	.ops = &dummy_ck_ops,

	.flags = CLK_IS_BASIC,

};

struct clk dummy_ck = {

	.core = &dummy_ck_core,

};

arch/arm/mach-omap2/dpll3xxx.c

+6 −5
Original line number Diff line number Diff line
@@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw) 
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	int r;

	struct dpll_data *dd;

	struct clk *parent;

	struct clk_hw *parent;



	dd = clk->dpll_data;

	if (!dd)
@@ -427,13 +427,13 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw) 
		}

	}



	parent = __clk_get_parent(hw->clk);

	parent = __clk_get_hw(__clk_get_parent(hw->clk));



	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {

		WARN_ON(parent != dd->clk_bypass);

		WARN_ON(parent != __clk_get_hw(dd->clk_bypass));

		r = _omap3_noncore_dpll_bypass(clk);

	} else {

		WARN_ON(parent != dd->clk_ref);

		WARN_ON(parent != __clk_get_hw(dd->clk_ref));

		r = _omap3_noncore_dpll_lock(clk);

	}
@@ -549,7 +549,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (!dd)

		return -EINVAL;



	if (__clk_get_parent(hw->clk) != dd->clk_ref)

	if (__clk_get_hw(__clk_get_parent(hw->clk)) !=

	    __clk_get_hw(dd->clk_ref))

		return -EINVAL;



	if (dd->last_rounded_rate == 0)

drivers/clk/clk.c

+406 −225

File changed.

Preview size limit exceeded, changes collapsed.