Loading arch/arm/boot/dts/qcom/msmfalcon.dtsi +4 −2 Original line number Diff line number Diff line Loading @@ -410,8 +410,10 @@ }; clock_gcc: clock-controller@100000 { compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; compatible = "qcom,gcc-msmfalcon"; reg = <0x100000 0x94000>; vdd_dig-supply = <&pm2falcon_s3_level>; vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; Loading arch/arm/boot/dts/qcom/msmtriton.dtsi +4 −2 Original line number Diff line number Diff line Loading @@ -340,8 +340,10 @@ }; clock_gcc: clock-controller@100000 { compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; compatible = "qcom,gcc-msmfalcon"; reg = <0x100000 0x94000>; vdd_dig-supply = <&pm2falcon_s3_level>; vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
arch/arm/boot/dts/qcom/msmfalcon.dtsi +4 −2 Original line number Diff line number Diff line Loading @@ -410,8 +410,10 @@ }; clock_gcc: clock-controller@100000 { compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; compatible = "qcom,gcc-msmfalcon"; reg = <0x100000 0x94000>; vdd_dig-supply = <&pm2falcon_s3_level>; vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; Loading
arch/arm/boot/dts/qcom/msmtriton.dtsi +4 −2 Original line number Diff line number Diff line Loading @@ -340,8 +340,10 @@ }; clock_gcc: clock-controller@100000 { compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; compatible = "qcom,gcc-msmfalcon"; reg = <0x100000 0x94000>; vdd_dig-supply = <&pm2falcon_s3_level>; vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; Loading