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Commit 02368c20 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Kyle Yan
Browse files

clk: msm: clock: Include logic to treat votable clocks/GDSCs differently 



On MSMCOBALT, the votable GDSCs might take longer to enable/disable
depending on a number of factors including if another entity outside
of HLOS tried disabling the GDSC at the same time that HLOS tried to
enable it. Add a higher polling timeout to accommodate this.
In addition, add flags to branch clocks which might be controlled via
the voting registers so that the driver does not print out a warning
if these clocks do not turn off even after removing the SW vote.

CRs-Fixed: 1027807
Change-Id: I044ca5209c364d4bfb4f3bd504cdcb87021fd010
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent ee014071

arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
		regulator-name = "gdsc_hlos1_vote_lpass_adsp";

		reg = <0x17d034 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};
@@ -47,6 +48,7 @@ 
		regulator-name = "gdsc_hlos1_vote_lpass_core";

		reg = <0x17d038 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};
@@ -125,6 +127,7 @@ 
		      <0x5066008 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};

drivers/clk/msm/clock-gcc-cobalt.c

+4 −0
Original line number Diff line number Diff line
@@ -1594,6 +1594,7 @@ static struct branch_clk gcc_bimc_gfx_clk = { 
	.cbcr_reg = GCC_BIMC_GFX_CBCR,

	.has_sibling = 1,

	.check_enable_bit = true,

	.no_halt_check_on_disable = true,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_bimc_gfx_clk",
@@ -1642,6 +1643,7 @@ static struct branch_clk gcc_gpu_bimc_gfx_clk = { 
	.cbcr_reg = GCC_GPU_BIMC_GFX_CBCR,

	.has_sibling = 1,

	.check_enable_bit = true,

	.no_halt_check_on_disable = true,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_gpu_bimc_gfx_clk",
@@ -1664,6 +1666,8 @@ static struct branch_clk gcc_gpu_bimc_gfx_src_clk = { 
static struct branch_clk gcc_gpu_cfg_ahb_clk = {

	.cbcr_reg = GCC_GPU_CFG_AHB_CBCR,

	.has_sibling = 1,

	.check_enable_bit = true,

	.no_halt_check_on_disable = true,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_gpu_cfg_ahb_clk",

drivers/clk/msm/clock-mmss-cobalt.c

+3 −0
Original line number Diff line number Diff line
@@ -1095,6 +1095,7 @@ static struct branch_clk mmss_bimc_smmu_ahb_clk = { 
	.cbcr_reg = MMSS_BIMC_SMMU_AHB_CBCR,

	.has_sibling = 1,

	.check_enable_bit = true,

	.no_halt_check_on_disable = true,

	.base = &virt_base,

	.c = {

		.dbg_name = "mmss_bimc_smmu_ahb_clk",
@@ -1107,6 +1108,7 @@ static struct branch_clk mmss_bimc_smmu_axi_clk = { 
	.cbcr_reg = MMSS_BIMC_SMMU_AXI_CBCR,

	.has_sibling = 1,

	.check_enable_bit = true,

	.no_halt_check_on_disable = true,

	.base = &virt_base,

	.c = {

		.dbg_name = "mmss_bimc_smmu_axi_clk",
@@ -2069,6 +2071,7 @@ static struct branch_clk mmss_mnoc_ahb_clk = { 
	.cbcr_reg = MMSS_MNOC_AHB_CBCR,

	.has_sibling = 0,

	.check_enable_bit = true,

	.no_halt_check_on_disable = true,

	.base = &virt_base,

	.c = {

		.dbg_name = "mmss_mnoc_ahb_clk",