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Commit ed302e84 authored by Yan He's avatar Yan He
Browse files

msm: pcie: Add the option to support L1ss 



L1 sub-states (L1ss) feature of PCIe is optional on targets. Add the
option to enable this feature or not.

Change-Id: I41347e046c81d5e9e9d6baac9324d18b7b83de2b
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent eac09cb3

Documentation/devicetree/bindings/pci/msm_pcie.txt

+5 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ Optional Properties: 
				"pcie_0_ldo";

  - max-clock-frequency-hz: list of the maximum operating frequencies stored

				in the same order of clock names;

  - qti,l1ss-supported: L1 sub-states (L1ss) is supported.

  - qti,aux-clk-sync: The AUX clock is synchronous to the Core clock to

    support L1ss.



Example:
@@ -101,4 +104,6 @@ Example: 
				"pcie_0_ldo";

		max-clock-frequency-hz = <125000000>, <0>, <1000000>,

						<0>, <0>, <0>, <0>;

		qti,l1ss-supported;

		qti,aux-clk-sync;

	};

arch/arm/mach-msm/pcie.c

+15 −2
Original line number Diff line number Diff line
@@ -676,7 +676,9 @@ static void msm_pcie_config_l1ss(u32 rc_idx) 
		readl_relaxed(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG));



	/* Enable the AUX Clock and the Core Clk to be synchronous for L1SS*/

	msm_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, BIT(3), 0);

	if (!dev->aux_clk_sync)

		msm_pcie_write_mask(dev->parf +

				PCIE20_PARF_SYS_CTRL, BIT(3), 0);



	/* Enable L1SS on RC */

	msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, 0,
@@ -1040,7 +1042,7 @@ static int msm_pcie_enable(u32 rc_idx, u32 options) 


	msm_pcie_config_msi_controller(dev);



	if (msm_pcie_dev[rc_idx].vreg_n == MSM_PCIE_MAX_VREG)

	if (dev->l1ss_supported)

		msm_pcie_config_l1ss(rc_idx);



	if (options & PM_IRQ) {
@@ -1201,6 +1203,17 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG("RC index is %d.", rc_idx);

	}



	msm_pcie_dev[rc_idx].l1ss_supported =

		of_property_read_bool((&pdev->dev)->of_node,

				"qti,l1ss-supported");

	PCIE_DBG("L1ss is %s supported.\n",

		msm_pcie_dev[rc_idx].l1ss_supported ? "" : "not");

	msm_pcie_dev[rc_idx].aux_clk_sync =

		of_property_read_bool((&pdev->dev)->of_node,

				"qti,aux-clk-sync");

	PCIE_DBG("AUX clock is %s synchronous to Core clock.\n",

		msm_pcie_dev[rc_idx].aux_clk_sync ? "" : "not");



	msm_pcie_dev[rc_idx].pdev = pdev;

	msm_pcie_dev[rc_idx].vreg_n = 0;

	msm_pcie_dev[rc_idx].gpio_n = 0;

arch/arm/mach-msm/pcie.h

+3 −0
Original line number Diff line number Diff line
@@ -164,6 +164,9 @@ struct msm_pcie_dev_t { 
	enum msm_pcie_link_status    link_status;

	bool                         user_suspend;

	struct pci_saved_state	     *saved_state;



	bool                         l1ss_supported;

	bool                         aux_clk_sync;

};



extern void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev);