Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cb5485a0 authored by Paul Gortmaker's avatar Paul Gortmaker Committed by Kumar Gala
Browse files

powerpc/85xx: sbc8548 - fixup of PCI-e related DTS fields 



The PCI-e addressing was originally patterned of the MPC8548CDS
which has PCI1, PCI2, and PCI-e.  Since this board only has
PCI1 and PCI-e, it makes more sense to be similar to the MPC8568MDS
board.  This does that by cutting the PCI/PCI-e I/O sizes from
16MB to 8MB and pulling the PCI-e I/O range back to 0xe280_0000
(the hole where PCI2 I/O would have been).

This also fixes a typo where an extra zero made an 8MB range a 128MB
range, removes the hole left by PCI2 from the aliases, and sets the
clocks to match the oscillators that are actually on the board.

With accompanying u-boot updates, PCI-e has been validated with
both a sky2 card (1148:9e00) and an e1000 card (8086:108b).

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 38634e67

arch/powerpc/boot/dts/sbc8548.dts

+8 −9
Original line number Original line Diff line number Diff line
@@ -26,8 +26,7 @@ 
		serial0 = &serial0;

		serial0 = &serial0;

		serial1 = &serial1;

		serial1 = &serial1;

		pci0 = &pci0;

		pci0 = &pci0;

		/* pci1 doesn't have a corresponding physical connector */

		pci1 = &pci1;

		pci2 = &pci2;

	};

	};





	cpus {

	cpus {
@@ -381,7 +380,7 @@ 
		bus-range = <0 0>;

		bus-range = <0 0>;

		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000

		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;

			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;

		clock-frequency = <66666666>;

		clock-frequency = <66000000>;

		#interrupt-cells = <1>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#size-cells = <2>;

		#address-cells = <3>;

		#address-cells = <3>;
@@ -390,7 +389,7 @@ 
		device_type = "pci";

		device_type = "pci";

	};

	};





	pci2: pcie@e000a000 {

	pci1: pcie@e000a000 {

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

		interrupt-map = <
@@ -403,9 +402,9 @@ 
		interrupt-parent = <&mpic>;

		interrupt-parent = <&mpic>;

		interrupts = <0x1a 0x2>;

		interrupts = <0x1a 0x2>;

		bus-range = <0x0 0xff>;

		bus-range = <0x0 0xff>;

		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000

		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;

			  0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;

		clock-frequency = <33333333>;

		clock-frequency = <33000000>;

		#interrupt-cells = <1>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#size-cells = <2>;

		#address-cells = <3>;

		#address-cells = <3>;
@@ -419,11 +418,11 @@ 
			device_type = "pci";

			device_type = "pci";

			ranges = <0x02000000 0x0 0xa0000000

			ranges = <0x02000000 0x0 0xa0000000

				  0x02000000 0x0 0xa0000000

				  0x02000000 0x0 0xa0000000

				  0x0 0x20000000

				  0x0 0x10000000





				  0x01000000 0x0 0x00000000

				  0x01000000 0x0 0x00000000

				  0x01000000 0x0 0x00000000

				  0x01000000 0x0 0x00000000

				  0x0 0x08000000>;

				  0x0 0x00800000>;

		};

		};

	};

	};

};
 
};