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Commit 6abe6224 authored by Rajesh Kemisetti's avatar Rajesh Kemisetti Committed by Lynus Vaz
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msm: kgsl: Add support for IOMMU-v2 



Add GPU self programming support for page table updates and
TLB flushes for IOMMU-v2. Also use VBIF recoverable HALT
feature to prevent the GPU from accessing the IOMMU while updates
are being done via dedicated AHB path.

Change-Id: If8c7f27f5437ff1c0be46a72f898eaa290e56024
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
Signed-off-by: default avatarLynus Vaz <lvaz@codeaurora.org>
parent faefe1ea

drivers/gpu/msm/a3xx_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -541,6 +541,9 @@ 
#define A3XX_VBIF_PERF_PWR_CNT2_LO 0x307b

#define A3XX_VBIF_PERF_PWR_CNT2_HI 0x307c



#define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL0 0x3800

#define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL1 0x3801



/* Bit flags for RBBM_CTL */

#define RBBM_RBBM_CTL_RESET_PWR_CTR0  BIT(0)

#define RBBM_RBBM_CTL_RESET_PWR_CTR1  BIT(1)
@@ -852,6 +855,9 @@ 
#define VBIF_AXI_TOTAL_BEATS 85

#define VBIF_DDR_TOTAL_CYCLES 110



/* VBIF Recoverable HALT bit value */

#define VBIF_RECOVERABLE_HALT_CTRL BIT(0)



/*

 * CP DEBUG settings for A3XX core:

 * DYNAMIC_CLK_DISABLE [27] - turn off the dynamic clock control

drivers/gpu/msm/adreno.c

+116 −1
Original line number Diff line number Diff line
@@ -1076,6 +1076,118 @@ static unsigned int _adreno_iommu_setstate_v1(struct kgsl_device *device, 
	return cmds - cmds_orig;

}



static unsigned int _adreno_iommu_setstate_v2(struct kgsl_device *device,

					unsigned int *cmds_orig,

					phys_addr_t pt_val,

					int num_iommu_units, uint32_t flags)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	phys_addr_t ttbr0_val;

	unsigned int reg_pt_val;

	unsigned int *cmds = cmds_orig;

	int i;

	unsigned int ttbr0, tlbiall, tlbstatus, tlbsync;



	cmds += adreno_add_idle_cmds(adreno_dev, cmds);



	for (i = 0; i < num_iommu_units; i++) {

		ttbr0_val = kgsl_mmu_get_default_ttbr0(&device->mmu,

				i, KGSL_IOMMU_CONTEXT_USER);

		ttbr0_val &= ~KGSL_IOMMU_CTX_TTBR0_ADDR_MASK;

		ttbr0_val |= (pt_val & KGSL_IOMMU_CTX_TTBR0_ADDR_MASK);

		if (flags & KGSL_MMUFLAGS_PTUPDATE) {



			ttbr0 = kgsl_mmu_get_reg_ahbaddr(&device->mmu, i,

						KGSL_IOMMU_CONTEXT_USER,

						KGSL_IOMMU_CTX_TTBR0) >> 2;



			/*

			 * glue commands together until next

			 * WAIT_FOR_ME

			 */

			cmds += adreno_wait_reg_eq(cmds,

				adreno_getreg(adreno_dev,

					ADRENO_REG_CP_WFI_PEND_CTR),

					1, 0xFFFFFFFF, 0xF);



			/* MMU-500 VBIF stall */

			*cmds++ = cp_type3_packet(CP_REG_RMW, 3);

			*cmds++ = A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL0;

			/* AND to unmask the HALT bit */

			*cmds++ = ~(VBIF_RECOVERABLE_HALT_CTRL);

			/* OR to set the HALT bit */

			*cmds++ = 0x1;



			/* Wait for acknowledgement */

			cmds += adreno_wait_reg_eq(cmds,

				A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL1,

					1, 0xFFFFFFFF, 0xF);



			/* set ttbr0 */

			if (sizeof(phys_addr_t) > sizeof(unsigned int)) {

				reg_pt_val = ttbr0_val & 0xFFFFFFFF;

				*cmds++ = cp_type3_packet(CP_REG_WR_NO_CTXT, 2);

				*cmds++ = ttbr0;

				*cmds++ = reg_pt_val;

				reg_pt_val = (unsigned int)

				((ttbr0_val & 0xFFFFFFFF00000000ULL) >> 32);

				*cmds++ = cp_type3_packet(CP_REG_WR_NO_CTXT, 2);

				*cmds++ = ttbr0 + 1;

				*cmds++ = reg_pt_val;

			} else {

				reg_pt_val = ttbr0_val;

				*cmds++ = cp_type3_packet(CP_REG_WR_NO_CTXT, 2);

				*cmds++ = ttbr0;

				*cmds++ = reg_pt_val;

			}



			/* MMU-500 VBIF unstall */

			*cmds++ = cp_type3_packet(CP_REG_RMW, 3);

			*cmds++ = A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL0;

			/* AND to unmask the HALT bit */

			*cmds++ = ~(VBIF_RECOVERABLE_HALT_CTRL);

			/* OR to reset the HALT bit */

			*cmds++ = 0;



			/* release all commands with wait_for_me */

			*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);

			*cmds++ = 0;



		}

		if (flags & KGSL_MMUFLAGS_TLBFLUSH) {

			tlbiall = kgsl_mmu_get_reg_ahbaddr(&device->mmu, i,

						KGSL_IOMMU_CONTEXT_USER,

						KGSL_IOMMU_CTX_TLBIALL) >> 2;

			*cmds++ = cp_type3_packet(CP_REG_WR_NO_CTXT, 2);

			*cmds++ = tlbiall;

			*cmds++ = 1;



			tlbsync = kgsl_mmu_get_reg_ahbaddr(&device->mmu, i,

						KGSL_IOMMU_CONTEXT_USER,

						KGSL_IOMMU_CTX_TLBSYNC) >> 2;

			*cmds++ = cp_type3_packet(CP_REG_WR_NO_CTXT, 2);

			*cmds++ = tlbsync;

			*cmds++ = 0;



			tlbstatus = kgsl_mmu_get_reg_ahbaddr(&device->mmu, i,

					KGSL_IOMMU_CONTEXT_USER,

					KGSL_IOMMU_CTX_TLBSTATUS) >> 2;

			if (adreno_is_a4xx(adreno_dev))

				cmds += adreno_wait_reg_mem(cmds, tlbstatus, 0,

					KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE, 0xF);

			else

				cmds += adreno_wait_reg_eq(cmds, tlbstatus, 0,

					KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE, 0xF);

			/* release all commands with wait_for_me */

			*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);

			*cmds++ = 0;

		}

	}



	cmds += adreno_add_idle_cmds(adreno_dev, cmds);



	return cmds - cmds_orig;

}

/**

 * adreno_use_default_setstate() - Use CPU instead of the GPU to manage the mmu?

 * @adreno_dev: the device
@@ -1133,7 +1245,10 @@ static int adreno_iommu_setstate(struct kgsl_device *device, 
		device->mmu.setstate_memory.gpuaddr +

		KGSL_IOMMU_SETSTATE_NOP_OFFSET);



	if (msm_soc_version_supports_iommu_v0())

	if (kgsl_msm_supports_iommu_v2())

		cmds += _adreno_iommu_setstate_v2(device, cmds, pt_val,

						num_iommu_units, flags);

	else if (msm_soc_version_supports_iommu_v0())

		cmds += _adreno_iommu_setstate_v0(device, cmds, pt_val,

						num_iommu_units, flags);

	else

drivers/gpu/msm/adreno_pm4types.h

+4 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2002,2007-2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2002,2007-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -150,6 +150,9 @@ 
/* test 2 memory locations to dword values specified */

#define CP_TEST_TWO_MEMS	0x71



/* Write register, ignoring context state for context sensitive registers */

#define CP_REG_WR_NO_CTXT  0x78



/* PFP waits until the FIFO between the PFP and the ME is empty */

#define CP_WAIT_FOR_ME		0x13

drivers/gpu/msm/kgsl_iommu.c

+15 −6
Original line number Diff line number Diff line
@@ -1167,7 +1167,12 @@ static int kgsl_set_register_map(struct kgsl_mmu *mmu) 


		if (!msm_soc_version_supports_iommu_v0())

			iommu_unit->iommu_halt_enable = 1;

		iommu_unit->ahb_base = data.physstart - mmu->device->reg_phys;



		if (kgsl_msm_supports_iommu_v2())

			iommu_unit->ahb_base = KGSL_IOMMU_V2_AHB_BASE;

		else

			iommu_unit->ahb_base =

				data.physstart - mmu->device->reg_phys;

	}

	iommu->unit_count = pdata_dev->iommu_count;

	return ret;
@@ -1335,7 +1340,8 @@ static unsigned int kgsl_iommu_get_reg_ahbaddr(struct kgsl_mmu *mmu, 
	if (iommu->iommu_reg_list[reg].ctx_reg)

		return iommu->iommu_units[iommu_unit].ahb_base +

			iommu->iommu_reg_list[reg].reg_offset +

			(ctx_id << KGSL_IOMMU_CTX_SHIFT) + iommu->ctx_offset;

			(ctx_id << KGSL_IOMMU_CTX_SHIFT) +

			iommu->ctx_ahb_offset;

	else

		return iommu->iommu_units[iommu_unit].ahb_base +

			iommu->iommu_reg_list[reg].reg_offset;
@@ -1412,15 +1418,18 @@ static int kgsl_iommu_init(struct kgsl_mmu *mmu) 
	if (status)

		goto done;



	if (kgsl_msm_supports_iommu_v2()) {

		iommu->iommu_reg_list = kgsl_iommuv1_reg;

		iommu->ctx_offset = KGSL_IOMMU_CTX_OFFSET_V2;

		iommu->ctx_ahb_offset = KGSL_IOMMU_CTX_AHB_OFFSET_V2;

	} else if (msm_soc_version_supports_iommu_v0()) {

		iommu->iommu_reg_list = kgsl_iommuv0_reg;

		iommu->ctx_offset = KGSL_IOMMU_CTX_OFFSET_V0;



	if (msm_soc_version_supports_iommu_v0()) {

		iommu->iommu_reg_list = kgsl_iommuv0_reg;

		iommu->ctx_offset = KGSL_IOMMU_CTX_OFFSET_V0;

		iommu->ctx_ahb_offset = KGSL_IOMMU_CTX_OFFSET_V0;

	} else {

		iommu->iommu_reg_list = kgsl_iommuv1_reg;

		iommu->ctx_offset = KGSL_IOMMU_CTX_OFFSET_V1;

		iommu->ctx_ahb_offset = KGSL_IOMMU_CTX_OFFSET_V1;

	}



	/* A nop is required in an indirect buffer when switching

drivers/gpu/msm/kgsl_iommu.h

+49 −1
Original line number Diff line number Diff line
@@ -17,8 +17,14 @@ 


#define KGSL_IOMMU_CTX_OFFSET_V0	0

#define KGSL_IOMMU_CTX_OFFSET_V1	0x8000

#define KGSL_IOMMU_CTX_OFFSET_V2	0x8000

#define KGSL_IOMMU_CTX_SHIFT		12



/* IOMMU V2 AHB base is fixed */

#define KGSL_IOMMU_V2_AHB_BASE		0xA000

/* IOMMU_V2 AHB base points to ContextBank0 */

#define KGSL_IOMMU_CTX_AHB_OFFSET_V2   0



/* TLBLKCR fields */

#define KGSL_IOMMU_TLBLKCR_LKE_MASK		0x00000001

#define KGSL_IOMMU_TLBLKCR_LKE_SHIFT		0
@@ -198,7 +204,9 @@ struct kgsl_iommu_unit { 
 * instance of the IOMMU driver

 * @device: Pointer to kgsl device

 * @ctx_offset: The context offset to be added to base address when

 * accessing IOMMU registers

 * accessing IOMMU registers from the CPU

 * @ctx_ahb_offset: The context offset to be added to base address when

 * accessing IOMMU registers from the GPU

 * @iommu_reg_list: List of IOMMU registers { offset, map, shift } array

 * @sync_lock_vars: Pointer to the IOMMU spinlock for serializing access to the

 * IOMMU registers
@@ -213,6 +221,7 @@ struct kgsl_iommu { 
	unsigned int unit_count;

	struct kgsl_device *device;

	unsigned int ctx_offset;

	unsigned int ctx_ahb_offset;

	struct kgsl_iommu_register_list *iommu_reg_list;

	struct remote_iommu_petersons_spinlock *sync_lock_vars;

	struct kgsl_memdesc sync_lock_desc;
@@ -244,4 +253,43 @@ struct kgsl_iommu_disable_clk_param { 
	unsigned int ts;

};



/*

 * kgsl_msm_supports_iommu_v2 - Checks whether IOMMU version is V2 or not

 *

 * Checks whether IOMMU version is V2 or not by parsing nodes.

 * Return: 1 if IOMMU v2 is found else 0

 */

#ifdef CONFIG_OF

static inline int _kgsl_msm_checks_iommu_v2(void)

{

	struct device_node *node;

	node = of_find_compatible_node(NULL, NULL, "qcom,msm-smmu-v2");

	if (node) {

		of_node_put(node);

		return 1;

	}

	return 0;

}

#endif



#if !defined(CONFIG_MSM_IOMMU_V0) && defined(CONFIG_OF)

static inline int kgsl_msm_supports_iommu_v2(void)

{

	static int soc_supports_v2 = -1;



	if (soc_supports_v2 != -1)

		return soc_supports_v2;

	if (_kgsl_msm_checks_iommu_v2()) {

		soc_supports_v2 = 1;

		return 1;

	}

	return 0;

}

#else

static inline int kgsl_msm_supports_iommu_v2(void)

{

	return 0;

}

#endif



#endif