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Commit 4ffa08d2 authored by Shubhraprakash Das's avatar Shubhraprakash Das
Browse files

msm: kgsl: Add snapshot support for A4XX 



Restructure the A3XX snapshot code such that the same code can
be used by A4XX for dumping A4XX snapshot.

Change-Id: I1a39c51e0ceffd9f7e8193ada1ecf2f977b5b496
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent 1fd34fba

drivers/gpu/msm/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -29,6 +29,7 @@ msm_adreno-y += \ 
	adreno_a4xx.o \

	adreno_a4xx.o \

	adreno_a3xx_trace.o \

	adreno_a3xx_trace.o \

	adreno_a3xx_snapshot.o \

	adreno_a3xx_snapshot.o \

	adreno_a4xx_snapshot.o \

	adreno.o \

	adreno.o \

	adreno_cp_parser.o

	adreno_cp_parser.o

drivers/gpu/msm/a4xx_reg.h

+324 −241
Original line number Original line Diff line number Diff line
@@ -45,38 +45,69 @@ enum a4xx_rb_perfctr_rb_sel { 
};

};





/* RBBM registers */

/* RBBM registers */

#define A4XX_RBBM_AHB_CMD		0x25

#define A4XX_RBBM_CLOCK_CTL			0x20

#define A4XX_RBBM_SP_HYST_CNT			0x21

#define A4XX_RBBM_SP_HYST_CNT			0x21

#define A4XX_RBBM_SW_RESET_CMD			0x22

#define A4XX_RBBM_SW_RESET_CMD			0x22



#define A4XX_RBBM_AHB_CTL0			0x23

#define A4XX_RBBM_AHB_CTL0			0x23

#define A4XX_RBBM_AHB_CTL1			0x24

#define A4XX_RBBM_AHB_CTL1			0x24

#define A4XX_RBBM_AHB_CMD			0x25

#define A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL		0x2b

#define A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL		0x2b

#define A4XX_RBBM_INTERFACE_HANG_INT_CTL	0x2f

#define A4XX_RBBM_INTERFACE_HANG_INT_CTL	0x2f

#define A4XX_RBBM_RBBM_CTL		0x3e

#define A4XX_RBBM_AHB_ERROR_STATUS	0x18f

#define A4XX_RBBM_STATUS		0x191

#define A4XX_RBBM_INT_CLEAR_CMD			0x36

#define A4XX_RBBM_INT_CLEAR_CMD			0x36

#define A4XX_RBBM_INT_0_MASK			0x37

#define A4XX_RBBM_INT_0_MASK			0x37

#define A4XX_RBBM_RBBM_CTL			0x3e

#define A4XX_RBBM_EXT_TRACE_BUS_CTL		0x49

#define A4XX_RBBM_EXT_TRACE_BUS_CTL		0x49



#define A4XX_RBBM_CFG_DEBBUS_SEL_A		0x4a

#define A4XX_RBBM_CFG_DEBBUS_SEL_A		0x4a

#define A4XX_RBBM_CFG_DEBBUS_SEL_B		0x4b

#define A4XX_RBBM_CFG_DEBBUS_SEL_B		0x4b

#define A4XX_RBBM_CFG_DEBBUS_SEL_C		0x4c

#define A4XX_RBBM_CFG_DEBBUS_SEL_C		0x4c

#define A4XX_RBBM_CFG_DEBBUS_SEL_D		0x4d

#define A4XX_RBBM_CFG_DEBBUS_SEL_D		0x4d

#define A4XX_RBBM_CFG_DEBBUS_SEL_PING_INDEX_SHIFT	0

#define A4XX_RBBM_CFG_DEBBUS_SEL_PING_BLK_SEL_SHIFT	8

#define A4XX_RBBM_CFG_DEBBUS_SEL_PONG_INDEX_SHIFT	16

#define A4XX_RBBM_CFG_DEBBUS_SEL_PONG_BLK_SEL_SHIFT	24



#define A4XX_RBBM_CFG_DEBBUS_CTLT		0x4e

#define A4XX_RBBM_CFG_DEBBUS_CTLT		0x4e

#define A4XX_RBBM_CFG_DEBBUS_CTLT_ENT_SHIFT		0

#define A4XX_RBBM_CFG_DEBBUS_CTLT_GRANU_SHIFT		12

#define A4XX_RBBM_CFG_DEBBUS_CTLT_SEGT_SHIFT		28



#define A4XX_RBBM_CFG_DEBBUS_CTLM		0x4f

#define A4XX_RBBM_CFG_DEBBUS_CTLM		0x4f

#define A4XX_RBBM_CFG_DEBBUS_CTLT_ENABLE_SHIFT		24



#define A4XX_RBBM_CFG_DEBBUS_OPL		0x50

#define A4XX_RBBM_CFG_DEBBUS_OPL		0x50

#define A4XX_RBBM_CFG_DEBBUS_OPE		0x51

#define A4XX_RBBM_CFG_DEBBUS_OPE		0x51

#define A4XX_RBBM_CFG_DEBBUS_IVTL_0		0x52

#define A4XX_RBBM_CFG_DEBBUS_IVTL_0		0x52

#define A4XX_RBBM_CFG_DEBBUS_IVTL_1		0x53

#define A4XX_RBBM_CFG_DEBBUS_IVTL_1		0x53

#define A4XX_RBBM_CFG_DEBBUS_IVTL_2		0x54

#define A4XX_RBBM_CFG_DEBBUS_IVTL_2		0x54

#define A4XX_RBBM_CFG_DEBBUS_IVTL_3		0x55

#define A4XX_RBBM_CFG_DEBBUS_IVTL_3		0x55



#define A4XX_RBBM_CFG_DEBBUS_MASKL_0		0x56

#define A4XX_RBBM_CFG_DEBBUS_MASKL_0		0x56

#define A4XX_RBBM_CFG_DEBBUS_MASKL_1		0x57

#define A4XX_RBBM_CFG_DEBBUS_MASKL_1		0x57

#define A4XX_RBBM_CFG_DEBBUS_MASKL_2		0x58

#define A4XX_RBBM_CFG_DEBBUS_MASKL_2		0x58

#define A4XX_RBBM_CFG_DEBBUS_MASKL_3		0x59

#define A4XX_RBBM_CFG_DEBBUS_MASKL_3		0x59





#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0		0x5a

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0		0x5a

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL0_SHIFT	0

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL1_SHIFT	4

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL2_SHIFT	8

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL3_SHIFT	12

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL4_SHIFT	16

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL5_SHIFT	20

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL6_SHIFT	24

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0_BYTEL7_SHIFT	28



#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1			0x5b

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1			0x5b

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL8_SHIFT	0

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL9_SHIFT	4

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL10_SHIFT	8

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL11_SHIFT	12

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL12_SHIFT	16

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL13_SHIFT	20

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL14_SHIFT	24

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1_BYTEL15_SHIFT	28



#define A4XX_RBBM_CFG_DEBBUS_IVTE_0		0x5c

#define A4XX_RBBM_CFG_DEBBUS_IVTE_0		0x5c

#define A4XX_RBBM_CFG_DEBBUS_IVTE_1		0x5d

#define A4XX_RBBM_CFG_DEBBUS_IVTE_1		0x5d

#define A4XX_RBBM_CFG_DEBBUS_IVTE_2		0x5e

#define A4XX_RBBM_CFG_DEBBUS_IVTE_2		0x5e
@@ -92,31 +123,13 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_RBBM_CFG_DEBBUS_IDX		0x93

#define A4XX_RBBM_CFG_DEBBUS_IDX		0x93

#define A4XX_RBBM_CFG_DEBBUS_CLRC		0x94

#define A4XX_RBBM_CFG_DEBBUS_CLRC		0x94

#define A4XX_RBBM_CFG_DEBBUS_LOADIVT		0x95

#define A4XX_RBBM_CFG_DEBBUS_LOADIVT		0x95

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF0        0x1a9



#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF1        0x1aa

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF2        0x1ab

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF3        0x1ac

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4        0x1ad

#define A4XX_RBBM_CFG_DEBBUS_MISR0	0x1ae

#define A4XX_RBBM_CFG_DEBBUS_MISR1	0x1af

#define A4XX_RBBM_CFG_COUNTER0		0x1a2

#define A4XX_RBBM_INT_0_STATUS		0x17d

#define A4XX_RBBM_PERFCTR_CTL		0x170

#define A4XX_RBBM_PERFCTR_LOAD_CMD0	0x171

#define A4XX_RBBM_PERFCTR_LOAD_CMD1	0x172

#define A4XX_RBBM_PERFCTR_LOAD_CMD2	0x173

#define A4XX_RBBM_GPU_BUSY_MASKED	0x17a

#define A4XX_RBBM_PERFCTR_PWR_1_LO	0x168

#define A4XX_RBBM_PERFCTR_CP_0_LO		0x9c

#define A4XX_RBBM_PERFCTR_CP_0_LO		0x9c

#define A4XX_RBBM_PERFCTR_CP_1_LO		0x9e

#define A4XX_RBBM_PERFCTR_CP_1_LO		0x9e

#define A4XX_RBBM_PERFCTR_RBBM_0_LO		0xac

#define A4XX_RBBM_PERFCTR_RBBM_0_LO		0xac

#define A4XX_RBBM_PERFCTR_RBBM_1_LO		0xae

#define A4XX_RBBM_PERFCTR_RBBM_1_LO		0xae

#define A4XX_RBBM_PERFCTR_RBBM_2_LO		0xb0

#define A4XX_RBBM_PERFCTR_RBBM_2_LO		0xb0

#define A4XX_RBBM_PERFCTR_RBBM_3_LO		0xb2

#define A4XX_RBBM_PERFCTR_RBBM_3_LO		0xb2

#define A4XX_RBBM_PERFCTR_RBBM_SEL_0	0x176

#define A4XX_RBBM_PERFCTR_RBBM_SEL_1	0x177

#define A4XX_RBBM_PERFCTR_RBBM_SEL_2	0x178

#define A4XX_RBBM_PERFCTR_RBBM_SEL_3	0x179





#define A4XX_RBBM_PERFCTR_PC_0_LO		0xb4

#define A4XX_RBBM_PERFCTR_PC_0_LO		0xb4

#define A4XX_RBBM_PERFCTR_PC_0_HI		0xb5

#define A4XX_RBBM_PERFCTR_PC_0_HI		0xb5
@@ -278,27 +291,49 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_RBBM_PERFCTR_PWR_0_HI		0x167

#define A4XX_RBBM_PERFCTR_PWR_0_HI		0x167

#define A4XX_RBBM_PERFCTR_PWR_1_LO		0x168

#define A4XX_RBBM_PERFCTR_PWR_1_LO		0x168

#define A4XX_RBBM_PERFCTR_PWR_1_HI		0x169

#define A4XX_RBBM_PERFCTR_PWR_1_HI		0x169

#define A4XX_RBBM_PERFCTR_CTL			0x170

#define A4XX_RBBM_PERFCTR_LOAD_CMD0		0x171

#define A4XX_RBBM_PERFCTR_LOAD_CMD1		0x172

#define A4XX_RBBM_PERFCTR_LOAD_CMD2		0x173

#define A4XX_RBBM_PERFCTR_RBBM_SEL_0		0x176

#define A4XX_RBBM_PERFCTR_RBBM_SEL_1		0x177

#define A4XX_RBBM_PERFCTR_RBBM_SEL_2		0x178

#define A4XX_RBBM_PERFCTR_RBBM_SEL_3		0x179

#define A4XX_RBBM_GPU_BUSY_MASKED		0x17a

#define A4XX_RBBM_INT_0_STATUS			0x17d

#define A4XX_RBBM_AHB_ERROR_STATUS		0x18f

#define A4XX_RBBM_STATUS			0x191

#define A4XX_RBBM_CFG_COUNTER0			0x1a2

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF0		0x1a9

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF1		0x1aa

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF2		0x1ab

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF3		0x1ac

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4		0x1ad

#define A4XX_RBBM_CFG_DEBBUS_MISR0		0x1ae

#define A4XX_RBBM_CFG_DEBBUS_MISR1		0x1af





/* CP registers */

/* CP registers */

#define A4XX_CP_SCRATCH_REG0		0x578

#define A4XX_CP_SCRATCH_UMASK		0x228

#define A4XX_CP_SCRATCH_ADDR		0x229

#define A4XX_CP_RB_BASE			0x200

#define A4XX_CP_RB_BASE			0x200

#define A4XX_CP_RB_CNTL			0x201

#define A4XX_CP_RB_CNTL			0x201

#define A4XX_CP_RB_WPTR			0x205

#define A4XX_CP_RB_RPTR_ADDR		0x203

#define A4XX_CP_RB_RPTR_ADDR		0x203

#define A4XX_CP_RB_RPTR			0x204

#define A4XX_CP_RB_RPTR			0x204

#define A4XX_CP_RB_WPTR			0x205

#define A4XX_CP_IB1_BASE		0x206

#define A4XX_CP_IB1_BASE		0x206

#define A4XX_CP_IB1_BUFSZ		0x207

#define A4XX_CP_IB1_BUFSZ		0x207

#define A4XX_CP_IB2_BASE		0x208

#define A4XX_CP_IB2_BASE		0x208

#define A4XX_CP_IB2_BUFSZ		0x209

#define A4XX_CP_IB2_BUFSZ		0x209

#define A4XX_CP_WFI_PEND_CTR		0x4d2

#define A4XX_CP_ROQ_ADDR		0x21C

#define A4XX_CP_ME_CNTL			0x22d

#define A4XX_CP_ROQ_DATA		0x21D

#define A4XX_CP_MEQ_ADDR		0x21E

#define A4XX_CP_MEQ_DATA		0x21F

#define A4XX_CP_MERCIU_ADDR		0x220

#define A4XX_CP_MERCIU_DATA		0x221

#define A4XX_CP_MERCIU_DATA2		0x222

#define A4XX_CP_PFP_UCODE_ADDR		0x223

#define A4XX_CP_PFP_UCODE_DATA		0x224

#define A4XX_CP_ME_RAM_WADDR		0x225

#define A4XX_CP_ME_RAM_WADDR		0x225

#define A4XX_CP_ME_RAM_RADDR		0x226

#define A4XX_CP_ME_RAM_RADDR		0x226

#define A4XX_CP_ME_RAM_DATA		0x227

#define A4XX_CP_ME_RAM_DATA		0x227

#define A4XX_CP_PFP_UCODE_ADDR		0x223

#define A4XX_CP_PFP_UCODE_DATA		0x224





#define A4XX_CP_DEBUG			0x22e

#define A4XX_CP_DEBUG			0x22e

/*

/*
@@ -308,9 +343,17 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_CP_DEBUG_DEFAULT (1 << 25)

#define A4XX_CP_DEBUG_DEFAULT (1 << 25)





#define A4XX_CP_PROTECT_CTRL		0x250

#define A4XX_CP_PROTECT_CTRL		0x250

#define A4XX_CP_DEBUG			0x22e

#define A4XX_CP_SCRATCH_UMASK		0x228

#define A4XX_CP_SCRATCH_ADDR		0x229

#define A4XX_CP_ME_CNTL			0x22d

#define A4XX_CP_STATE_DEBUG_INDEX	0x22F

#define A4XX_CP_STATE_DEBUG_DATA	0x230

#define A4XX_CP_PROTECT_CTRL		0x250

#define A4XX_CP_ME_STATUS		0x4D1

#define A4XX_CP_WFI_PEND_CTR		0x4d2

#define A4XX_CP_PERFCTR_CP_SEL_0	0x500

#define A4XX_CP_PERFCTR_CP_SEL_0	0x500

#define A4XX_CP_PERFCTR_CP_SEL_1	0x501

#define A4XX_CP_PERFCTR_CP_SEL_1	0x501

#define A4XX_CP_SCRATCH_REG0		0x578





/* SP registers */

/* SP registers */

#define A4XX_SP_VS_OBJ_START		0x22e1

#define A4XX_SP_VS_OBJ_START		0x22e1
@@ -527,6 +570,7 @@ enum a4xx_pc_perfctr_pc_sel { 
#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_5	0xe0b

#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_5	0xe0b

#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_6	0xe0c

#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_6	0xe0c

#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_7	0xe0d

#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_7	0xe0d

#define A4XX_HLSQ_SPTP_RDSEL		0xe30





enum a4xx_hlsq_perfctr_hlsq_sel {

enum a4xx_hlsq_perfctr_hlsq_sel {

	HLSQ_SP_VS_STAGE_CONSTANT = 0x0,

	HLSQ_SP_VS_STAGE_CONSTANT = 0x0,
@@ -597,4 +641,43 @@ enum a4xx_tpl1_perfctr_tp_sel { 
	TP_LATENCY_TRANS = 0x13,

	TP_LATENCY_TRANS = 0x13,

};

};





/* Enum for debug bus */

enum a4xx_rbbm_debbus_id {

	A4XX_RBBM_DEBBUS_CP_ID = 0x1,

	A4XX_RBBM_DEBBUS_RBBM_ID = 0x2,

	A4XX_RBBM_DEBBUS_VBIF_ID = 0x3,

	A4XX_RBBM_DEBBUS_HLSQ_ID = 0x4,

	A4XX_RBBM_DEBBUS_UCHE_ID = 0x5,

	A4XX_RBBM_DEBBUS_DPM_ID  = 0x6,

	A4XX_RBBM_DEBBUS_TESS_ID = 0x7,

	A4XX_RBBM_DEBBUS_PC_ID   = 0x8,

	A4XX_RBBM_DEBBUS_VFD_ID  = 0x9,

	A4XX_RBBM_DEBBUS_VPC_ID  = 0xa,

	A4XX_RBBM_DEBBUS_TSE_ID  = 0xb,

	A4XX_RBBM_DEBBUS_RAS_ID  = 0xc,

	A4XX_RBBM_DEBBUS_VSC_ID  = 0xd,

	A4XX_RBBM_DEBBUS_COM_ID  = 0xe,

	A4XX_RBBM_DEBBUS_DCOM_ID = 0xf,

	A4XX_RBBM_DEBBUS_SP_0_ID = 0x10,

	A4XX_RBBM_DEBBUS_SP_1_ID = 0x11,

	A4XX_RBBM_DEBBUS_SP_2_ID = 0x12,

	A4XX_RBBM_DEBBUS_SP_3_ID = 0x13,

	A4XX_RBBM_DEBBUS_TPL1_0_ID = 0x18,

	A4XX_RBBM_DEBBUS_TPL1_1_ID = 0x19,

	A4XX_RBBM_DEBBUS_TPL1_2_ID = 0x1a,

	A4XX_RBBM_DEBBUS_TPL1_3_ID = 0x1b,

	A4XX_RBBM_DEBBUS_RB_0_ID = 0x20,

	A4XX_RBBM_DEBBUS_RB_1_ID = 0x21,

	A4XX_RBBM_DEBBUS_RB_2_ID = 0x22,

	A4XX_RBBM_DEBBUS_RB_3_ID = 0x23,

	A4XX_RBBM_DEBBUS_MARB_0_ID = 0x28,

	A4XX_RBBM_DEBBUS_MARB_1_ID = 0x29,

	A4XX_RBBM_DEBBUS_MARB_2_ID = 0x2a,

	A4XX_RBBM_DEBBUS_MARB_3_ID = 0x2b,

	A4XX_RBBM_DEBBUS_CCU_0_ID = 0x30,

	A4XX_RBBM_DEBBUS_CCU_1_ID = 0x31,

	A4XX_RBBM_DEBBUS_CCU_2_ID = 0x32,

	A4XX_RBBM_DEBBUS_CCU_3_ID = 0x33

};



#endif /* _A4XX_REG_H */
 
#endif /* _A4XX_REG_H */

drivers/gpu/msm/adreno.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include "adreno_trace.h"

#include "adreno_trace.h"





#include "a3xx_reg.h"

#include "a3xx_reg.h"

#include "adreno_a3xx_snapshot.h"





#define DRIVER_VERSION_MAJOR   3

#define DRIVER_VERSION_MAJOR   3

#define DRIVER_VERSION_MINOR   1

#define DRIVER_VERSION_MINOR   1
@@ -1598,6 +1599,16 @@ static int adreno_init(struct kgsl_device *device) 
		adreno_a3xx_pwron_fixup_init(adreno_dev);

		adreno_a3xx_pwron_fixup_init(adreno_dev);





	set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);

	set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);



	/* Adjust snapshot section sizes according to core */

	if ((adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev))) {

		adreno_dev->gpudev->snapshot_data->sect_sizes->cp_state_deb =

					A320_SNAPSHOT_CP_STATE_SECTION_SIZE;

		adreno_dev->gpudev->snapshot_data->sect_sizes->roq =

					A320_SNAPSHOT_ROQ_SECTION_SIZE;

		adreno_dev->gpudev->snapshot_data->sect_sizes->cp_merciu =

					A320_SNAPSHOT_CP_MERCIU_SECTION_SIZE;

	}

done:

done:

	return ret;

	return ret;

}

}

drivers/gpu/msm/adreno.h

+46 −0
Original line number Original line Diff line number Diff line
@@ -301,6 +301,13 @@ enum adreno_regs { 
	ADRENO_REG_CP_IB2_BUFSZ,

	ADRENO_REG_CP_IB2_BUFSZ,

	ADRENO_REG_CP_TIMESTAMP,

	ADRENO_REG_CP_TIMESTAMP,

	ADRENO_REG_CP_ME_RAM_RADDR,

	ADRENO_REG_CP_ME_RAM_RADDR,

	ADRENO_REG_CP_ROQ_ADDR,

	ADRENO_REG_CP_ROQ_DATA,

	ADRENO_REG_CP_MERCIU_ADDR,

	ADRENO_REG_CP_MERCIU_DATA,

	ADRENO_REG_CP_MERCIU_DATA2,

	ADRENO_REG_CP_MEQ_ADDR,

	ADRENO_REG_CP_MEQ_DATA,

	ADRENO_REG_SCRATCH_ADDR,

	ADRENO_REG_SCRATCH_ADDR,

	ADRENO_REG_SCRATCH_UMSK,

	ADRENO_REG_SCRATCH_UMSK,

	ADRENO_REG_SCRATCH_REG2,

	ADRENO_REG_SCRATCH_REG2,
@@ -317,6 +324,7 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_AHB_CMD,

	ADRENO_REG_RBBM_AHB_CMD,

	ADRENO_REG_RBBM_INT_CLEAR_CMD,

	ADRENO_REG_RBBM_INT_CLEAR_CMD,

	ADRENO_REG_RBBM_SW_RESET_CMD,

	ADRENO_REG_RBBM_SW_RESET_CMD,

	ADRENO_REG_RBBM_CLOCK_CTL,

	ADRENO_REG_VPC_DEBUG_RAM_SEL,

	ADRENO_REG_VPC_DEBUG_RAM_SEL,

	ADRENO_REG_VPC_DEBUG_RAM_READ,

	ADRENO_REG_VPC_DEBUG_RAM_READ,

	ADRENO_REG_VSC_PIPE_DATA_ADDRESS_0,

	ADRENO_REG_VSC_PIPE_DATA_ADDRESS_0,
@@ -430,6 +438,43 @@ struct adreno_irq { 
	int funcs_count;

	int funcs_count;

};

};





/*

 * struct adreno_debugbus_block - Holds info about debug buses of a chip

 * @block_id: Bus identifier

 * @dwords: Number of dwords of data that this block holds

 */

struct adreno_debugbus_block {

	unsigned int block_id;

	unsigned int dwords;

};



/*

 * struct adreno_snapshot_section_sizes - Structure holding the size of

 * different sections dumped during device snapshot

 * @cp_state_deb_size: Debug data section size

 * @vpc_mem_size: VPC memory section size

 * @cp_meq_size: CP MEQ size

 * @shader_mem_size: Size of shader memory of 1 shader section

 * @cp_merciu_size: CP MERCIU size

 * @roq_size: ROQ size

 */

struct adreno_snapshot_sizes {

	int cp_state_deb;

	int vpc_mem;

	int cp_meq;

	int shader_mem;

	int cp_merciu;

	int roq;

};



/*

 * struct adreno_snapshot_data - Holds data used in snapshot

 * @sect_sizes: Has sections sizes

 */

struct adreno_snapshot_data {

	struct adreno_snapshot_sizes *sect_sizes;

};



struct adreno_gpudev {

struct adreno_gpudev {

	/*

	/*

	 * These registers are in a different location on different devices,

	 * These registers are in a different location on different devices,
@@ -442,6 +487,7 @@ struct adreno_gpudev { 
	struct adreno_perfcounters *perfcounters;

	struct adreno_perfcounters *perfcounters;

	const struct adreno_invalid_countables

	const struct adreno_invalid_countables

			*invalid_countables;

			*invalid_countables;

	struct adreno_snapshot_data *snapshot_data;





	struct adreno_coresight *coresight;

	struct adreno_coresight *coresight;

drivers/gpu/msm/adreno_a3xx.c

+26 −0
Original line number Original line Diff line number Diff line
@@ -4655,6 +4655,13 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_RADDR, A3XX_CP_ME_RAM_RADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_RADDR, A3XX_CP_ME_RAM_RADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_ADDR, A3XX_CP_SCRATCH_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_ADDR, A3XX_CP_SCRATCH_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_UMSK, A3XX_CP_SCRATCH_UMSK),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_UMSK, A3XX_CP_SCRATCH_UMSK),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_ADDR, A4XX_CP_ROQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_DATA, A3XX_CP_ROQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MERCIU_ADDR, A3XX_CP_MERCIU_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MERCIU_DATA, A3XX_CP_MERCIU_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MERCIU_DATA2, A3XX_CP_MERCIU_DATA2),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A3XX_CP_MEQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A3XX_CP_MEQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A3XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A3XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A3XX_RBBM_PERFCTR_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A3XX_RBBM_PERFCTR_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,
@@ -4670,6 +4677,7 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_AHB_CMD, A3XX_RBBM_AHB_CMD),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_AHB_CMD, A3XX_RBBM_AHB_CMD),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_CLEAR_CMD,

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_CLEAR_CMD,

				A3XX_RBBM_INT_CLEAR_CMD),

				A3XX_RBBM_INT_CLEAR_CMD),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_CLOCK_CTL, A3XX_RBBM_CLOCK_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_VPC_DEBUG_RAM_SEL,

	ADRENO_REG_DEFINE(ADRENO_REG_VPC_DEBUG_RAM_SEL,

				A3XX_VPC_VPC_DEBUG_RAM_SEL),

				A3XX_VPC_VPC_DEBUG_RAM_SEL),

	ADRENO_REG_DEFINE(ADRENO_REG_VPC_DEBUG_RAM_READ,

	ADRENO_REG_DEFINE(ADRENO_REG_VPC_DEBUG_RAM_READ,
@@ -4709,10 +4717,28 @@ const struct adreno_reg_offsets a3xx_reg_offsets = { 
	.offset_0 = ADRENO_REG_REGISTER_MAX,

	.offset_0 = ADRENO_REG_REGISTER_MAX,

};

};





/*

 * Defined the size of sections dumped in snapshot, these values

 * may change after initialization based on the specific core

 */

static struct adreno_snapshot_sizes a3xx_snap_sizes = {

	.cp_state_deb = 0x14,

	.vpc_mem = 512,

	.cp_meq = 16,

	.shader_mem = 0x4000,

	.cp_merciu = 0,

	.roq = 128,

};



static struct adreno_snapshot_data a3xx_snapshot_data = {

	.sect_sizes = &a3xx_snap_sizes,

};



struct adreno_gpudev adreno_a3xx_gpudev = {

struct adreno_gpudev adreno_a3xx_gpudev = {

	.reg_offsets = &a3xx_reg_offsets,

	.reg_offsets = &a3xx_reg_offsets,

	.perfcounters = &a3xx_perfcounters,

	.perfcounters = &a3xx_perfcounters,

	.irq = &a3xx_irq,

	.irq = &a3xx_irq,

	.snapshot_data = &a3xx_snapshot_data,





	.ctxt_create = a3xx_drawctxt_create,

	.ctxt_create = a3xx_drawctxt_create,

	.rb_init = a3xx_rb_init,

	.rb_init = a3xx_rb_init,