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Commit 44f16fcf authored by Matthew McClintock's avatar Matthew McClintock Committed by Kumar Gala
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powerpc/85xx: issue 15 EOI after core reset for FSL CoreNet devices 



This is listed as a requirement for Freescale CoreNet based devices  (e.g
p4080ds with MPIC v4.x) after issuing a core reset to properly clear pending
interrupts.

Signed-off-by: default avatarMatthew McClintock <msm@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent cfadd838

arch/powerpc/sysdev/mpic.c

+10 −0
Original line number Diff line number Diff line
@@ -1748,6 +1748,7 @@ void mpic_reset_core(int cpu) 
	struct mpic *mpic = mpic_primary;

	u32 pir;

	int cpuid = get_hard_smp_processor_id(cpu);

	int i;



	/* Set target bit for core reset */

	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
@@ -1759,6 +1760,15 @@ void mpic_reset_core(int cpu) 
	pir &= ~(1 << cpuid);

	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);

	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));



	/* Perform 15 EOI on each reset core to clear pending interrupts.

	 * This is required for FSL CoreNet based devices */

	if (mpic->flags & MPIC_FSL) {

		for (i = 0; i < 15; i++) {

			_mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],

				      MPIC_CPU_EOI, 0);

		}

	}

}

#endif /* CONFIG_SMP */