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Commit 2a1b0bc3 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "usb: xhci-msm-hsic: Add support to disable HW clock gating"

parents 35105767 d314749a

Documentation/devicetree/bindings/usb/msm-xhci-hsic.txt

+2 −0
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ Optional properties : 
    - qcom,msm_bus,num_cases

    - qcom,msm_bus,num_paths

    - qcom,msm_bus,vectors

- qti,disable-hw-clk-gating: If present then hw clock gating in controller

  is disabled. Internal clock gating is enabled by default in hw.



Example MSM HSIC XHCI controller device node :

	xhci_hsic_host: qcom,xhci-msm-hsic@0xf9c00000 {

drivers/usb/host/xhci-msm-hsic.c

+6 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define TLMM_GPIO_HSIC_STROBE_PAD_CTL	(MSM_TLMM_BASE + 0x2050)

#define TLMM_GPIO_HSIC_DATA_PAD_CTL	(MSM_TLMM_BASE + 0x2054)



#define GCTL_DSBLCLKGTNG	BIT(0)

#define GCTL_CORESOFTRESET	BIT(11)



/* Global USB2 PHY Configuration Register */
@@ -942,6 +943,11 @@ static int mxhci_hsic_probe(struct platform_device *pdev) 
	reg |= CTRLREG_PLL_CTRL_SLEEP | CTRLREG_PLL_CTRL_SUSP;

	writel_relaxed(reg, MSM_HSIC_CTRL_REG);



	if (of_property_read_bool(node, "qti,disable-hw-clk-gating")) {

		reg = readl_relaxed(MSM_HSIC_GCTL);

		writel_relaxed((reg | GCTL_DSBLCLKGTNG), MSM_HSIC_GCTL);

	}



	/* enable pwr event irq for LPM_IN_L2_IRQ */

	writel_relaxed(LPM_IN_L2_IRQ_MASK, MSM_HSIC_PWR_EVNT_IRQ_MASK);