msm: mdss: MISR changes for mdp3 (192281eb) · Commits · e / devices / android_kernel_sony_msm8994_rework

drivers/video/msm/mdss/mdp3.c

+104 −1

Original line number	Diff line number	Diff line
		@@ -38,7 +38,7 @@
		#include <linux/major.h>
		#include <linux/bootmem.h>
		#include <linux/memblock.h>

		#include <linux/iopoll.h>
		#include <mach/board.h>
		#include <mach/clk.h>
		#include <mach/hardware.h>
		@@ -55,6 +55,10 @@
		#include "mdp3_ppp.h"
		#include "mdss_debug.h"

		#define MISR_POLL_SLEEP 2000
		#define MISR_POLL_TIMEOUT 32000
		#define MDP3_REG_CAPTURED_DSI_PCLK_MASK 1

		#define MDP_CORE_HW_VERSION 0x03040310
		struct mdp3_hw_resource *mdp3_res;

		@@ -1983,6 +1987,105 @@ int mdp3_create_sysfs_link(struct device *dev)
		return rc;
		}

		int mdp3_misr_get(struct mdp_misr *misr_resp)
		{
		int result = 0, ret = -1;
		int crc = 0;
		pr_debug("%s CRC Capture on DSI\n", __func__);
		switch (misr_resp->block_id) {
		case DISPLAY_MISR_DSI0:
		MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_EN, 0);
		/* Sleep for one vsync after DSI video engine is disabled */
		msleep(20);
		/* Enable DSI_VIDEO_0 MISR Block */
		MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x20);
		/* Reset MISR Block */
		MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 1);
		/* Clear MISR capture done bit */
		MDP3_REG_WRITE(MDP3_REG_CAPTURED_DSI_PCLK, 0);
		/* Enable MDP DSI interface */
		MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_EN, 1);
		ret = readl_poll_timeout(mdp3_res->mdp_base +
		MDP3_REG_CAPTURED_DSI_PCLK, result,
		result & MDP3_REG_CAPTURED_DSI_PCLK_MASK,
		MISR_POLL_SLEEP, MISR_POLL_TIMEOUT);
		MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0);
		if (ret == 0) {
		/* Disable DSI MISR interface */
		MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x0);
		crc = MDP3_REG_READ(MDP3_REG_MISR_CAPT_VAL_DSI_PCLK);
		pr_debug("CRC Val %d\n", crc);
		} else {
		pr_err("CRC Read Timed Out\n");
		}
		break;

		case DISPLAY_MISR_DSI_CMD:
		/* Select DSI PCLK Domain */
		MDP3_REG_WRITE(MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS, 0x004);
		/* Select Block id DSI_CMD */
		MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x10);
		/* Reset MISR Block */
		MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 1);
		/* Drive Data on Test Bus */
		MDP3_REG_WRITE(MDP3_REG_EXPORT_MISR_DSI_PCLK, 0);
		/* Kikk off DMA_P */
		MDP3_REG_WRITE(MDP3_REG_DMA_P_START, 0x11);
		/* Wait for DMA_P Done */
		ret = readl_poll_timeout(mdp3_res->mdp_base +
		MDP3_REG_INTR_STATUS, result,
		result & MDP3_INTR_DMA_P_DONE_BIT,
		MISR_POLL_SLEEP, MISR_POLL_TIMEOUT);
		if (ret == 0) {
		crc = MDP3_REG_READ(MDP3_REG_MISR_CURR_VAL_DSI_PCLK);
		pr_debug("CRC Val %d\n", crc);
		} else {
		pr_err("CRC Read Timed Out\n");
		}
		break;

		default:
		pr_err("%s CRC Capture not supported\n", __func__);
		ret = -EINVAL;
		break;
		}

		misr_resp->crc_value[0] = crc;
		pr_debug("%s, CRC Capture on DSI Param Block = 0x%x, CRC 0x%x\n",
		__func__, misr_resp->block_id, misr_resp->crc_value[0]);
		return ret;
		}

		int mdp3_misr_set(struct mdp_misr *misr_req)
		{
		int ret = 0;
		pr_debug("%s Parameters Block = %d Cframe Count = %d CRC = %d\n",
		__func__, misr_req->block_id, misr_req->frame_count,
		misr_req->crc_value[0]);

		switch (misr_req->block_id) {
		case DISPLAY_MISR_DSI0:
		pr_debug("In the case DISPLAY_MISR_DSI0\n");
		MDP3_REG_WRITE(MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS, 1);
		MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x20);
		MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 0x1);
		break;

		case DISPLAY_MISR_DSI_CMD:
		pr_debug("In the case DISPLAY_MISR_DSI_CMD\n");
		MDP3_REG_WRITE(MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS, 1);
		MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x10);
		MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 0x1);
		break;

		default:
		pr_err("%s CRC Capture not supported\n", __func__);
		ret = -EINVAL;
		break;
		}
		return ret;
		}

		static int mdp3_probe(struct platform_device *pdev)
		{
		int rc;

drivers/video/msm/mdss/mdp3.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -190,6 +190,9 @@ int mdp3_parse_dt_splash(struct msm_fb_data_type *mfd);
		void mdp3_release_splash_memory(void);
		int mdp3_create_sysfs_link(struct device *dev);

		int mdp3_misr_set(struct mdp_misr *misr_req);
		int mdp3_misr_get(struct mdp_misr *misr_resp);

		#define MDP3_REG_WRITE(addr, val) writel_relaxed(val, mdp3_res->mdp_base + addr)
		#define MDP3_REG_READ(addr) readl_relaxed(mdp3_res->mdp_base + addr)

drivers/video/msm/mdss/mdp3_ctrl.c

+51 −4

Original line number	Diff line number	Diff line
		@@ -950,6 +950,32 @@ pan_error:
		mutex_unlock(&mdp3_session->lock);
		}

		static int mdp3_set_metadata(struct msm_fb_data_type *mfd,
		struct msmfb_metadata *metadata_ptr)
		{
		int ret = 0;
		switch (metadata_ptr->op) {
		case metadata_op_crc:
		ret = mdp3_ctrl_res_req_clk(mfd, 1);
		if (ret) {
		pr_err("failed to turn on mdp clks\n");
		return ret;
		}
		ret = mdp3_misr_set(&metadata_ptr->data.misr_request);
		ret = mdp3_ctrl_res_req_clk(mfd, 0);
		if (ret) {
		pr_err("failed to release mdp clks\n");
		return ret;
		}
		break;
		default:
		pr_warn("Unsupported request to MDP SET META IOCTL.\n");
		ret = -EINVAL;
		break;
		}
		return ret;
		}

		static int mdp3_get_metadata(struct msm_fb_data_type *mfd,
		struct msmfb_metadata *metadata)
		{
		@@ -965,8 +991,21 @@ static int mdp3_get_metadata(struct msm_fb_data_type *mfd,
		metadata->data.caps.vig_pipes = 0;
		metadata->data.caps.dma_pipes = 1;
		break;
		case metadata_op_crc:
		ret = mdp3_ctrl_res_req_clk(mfd, 1);
		if (ret) {
		pr_err("failed to turn on mdp clks\n");
		return ret;
		}
		ret = mdp3_misr_get(&metadata->data.misr_request);
		ret = mdp3_ctrl_res_req_clk(mfd, 0);
		if (ret) {
		pr_err("failed to release mdp clks\n");
		return ret;
		}
		break;
		default:
		pr_warn("Unsupported request to MDP META IOCTL.\n");
		pr_warn("Unsupported request to MDP GET META IOCTL.\n");
		ret = -EINVAL;
		break;
		}
		@@ -1427,11 +1466,19 @@ static int mdp3_ctrl_ioctl_handler(struct msm_fb_data_type *mfd,
		break;
		case MSMFB_METADATA_GET:
		rc = copy_from_user(&metadata, argp, sizeof(metadata));
		if (rc)
		return rc;
		if (!rc)
		rc = mdp3_get_metadata(mfd, &metadata);
		if (!rc)
		rc = copy_to_user(argp, &metadata, sizeof(metadata));
		if (rc)
		pr_err("mdp3_get_metadata failed (%d)\n", rc);
		break;
		case MSMFB_METADATA_SET:
		rc = copy_from_user(&metadata, argp, sizeof(metadata));
		if (!rc)
		rc = mdp3_set_metadata(mfd, &metadata);
		if (rc)
		pr_err("mdp3_set_metadata failed (%d)\n", rc);
		break;
		case MSMFB_OVERLAY_GET:
		rc = copy_from_user(req, argp, sizeof(*req));

drivers/video/msm/mdss/mdp3_hwio.h

+41 −0

Original line number	Diff line number	Diff line
		@@ -55,6 +55,7 @@

		#define MDP3_REG_HW_VERSION 0x0070
		#define MDP3_REG_SW_RESET 0x0074
		#define MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS 0x007C

		/EBI/
		#define MDP3_REG_EBI2_LCD0 0x003c
		@@ -117,6 +118,46 @@
		#define MDP3_REG_DMA_S_IBUF_Y_STRIDE 0xA000C
		#define MDP3_REG_DMA_S_OUT_XY 0xA0010

		/MISR/
		#define MDP3_REG_MODE_CLK 0x000D0000
		#define MDP3_REG_MISR_RESET_CLK 0x000D0004
		#define MDP3_REG_EXPORT_MISR_CLK 0x000D0008
		#define MDP3_REG_MISR_CURR_VAL_CLK 0x000D000C
		#define MDP3_REG_MODE_HCLK 0x000D0100
		#define MDP3_REG_MISR_RESET_HCLK 0x000D0104
		#define MDP3_REG_EXPORT_MISR_HCLK 0x000D0108
		#define MDP3_REG_MISR_CURR_VAL_HCLK 0x000D010C
		#define MDP3_REG_MODE_DCLK 0x000D0200
		#define MDP3_REG_MISR_RESET_DCLK 0x000D0204
		#define MDP3_REG_EXPORT_MISR_DCLK 0x000D0208
		#define MDP3_REG_MISR_CURR_VAL_DCLK 0x000D020C
		#define MDP3_REG_CAPTURED_DCLK 0x000D0210
		#define MDP3_REG_MISR_CAPT_VAL_DCLK 0x000D0214
		#define MDP3_REG_MODE_TVCLK 0x000D0300
		#define MDP3_REG_MISR_RESET_TVCLK 0x000D0304
		#define MDP3_REG_EXPORT_MISR_TVCLK 0x000D0308
		#define MDP3_REG_MISR_CURR_VAL_TVCLK 0x000D030C
		#define MDP3_REG_CAPTURED_TVCLK 0x000D0310
		#define MDP3_REG_MISR_CAPT_VAL_TVCLK 0x000D0314

		/* Select DSI operation type(CMD/VIDEO) */
		#define MDP3_REG_MODE_DSI_PCLK 0x000D0400
		#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_CMD 0x10
		#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_VIDEO1 0x20
		#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_VIDEO2 0x30
		/* RESET DSI MISR STATE */
		#define MDP3_REG_MISR_RESET_DSI_PCLK 0x000D0404

		/* For reading MISR State(1) and driving data on test bus(0) */
		#define MDP3_REG_EXPORT_MISR_DSI_PCLK 0x000D0408
		/* Read MISR signature */
		#define MDP3_REG_MISR_CURR_VAL_DSI_PCLK 0x000D040C

		/* MISR status Bit0 (1) Capture Done */
		#define MDP3_REG_CAPTURED_DSI_PCLK 0x000D0410
		#define MDP3_REG_MISR_CAPT_VAL_DSI_PCLK 0x000D0414
		#define MDP3_REG_MISR_TESTBUS_CAPT_VAL 0x000D0600

		/interface/
		#define MDP3_REG_LCDC_EN 0xE0000
		#define MDP3_REG_LCDC_HSYNC_CTL 0xE0004