Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ffd565a8 authored by Andreas Herrmann's avatar Andreas Herrmann Committed by Ingo Molnar
Browse files

x86: fixup config space size of CPU functions for AMD family 11h



Impact: extend allowed configuration space access on 11h CPUs from 256 to 4K

Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann3@amd.com>
Acked-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent de90add3
Loading
Loading
Loading
Loading
+14 −11
Original line number Original line Diff line number Diff line
@@ -496,21 +496,24 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
			  pci_siemens_interrupt_controller);
			  pci_siemens_interrupt_controller);


/*
/*
 * Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config
 * Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have
 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 * 4096 bytes configuration space for each function of their processor
 * access it.  Maybe we don't have a way to generate extended config space
 * configuration space.
 * accesses.   So check it
 */
 */
static void fam10h_pci_cfg_space_size(struct pci_dev *dev)
static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev)
{
{
	dev->cfg_size = pci_cfg_space_size_ext(dev);
	dev->cfg_size = pci_cfg_space_size_ext(dev);
}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size);


/*
/*
 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from