Loading arch/arm/boot/dts/qcom/msm8916-coresight.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,7 @@ interrupt-names = "byte-cntr-irq"; qcom,memory-size = <0x100000>; qcom,tmc-flush-powerdown; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -92,6 +93,9 @@ coresight-child-ports = <0>; coresight-default-sink; coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading @@ -124,6 +128,9 @@ coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <4>; qcom,funnel-save-restore; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading arch/arm/boot/dts/qcom/msm8939-coresight.dtsi +6 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ qcom,memory-size = <0x100000>; qcom,sg-enable; qcom,tmc-flush-powerdown; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -94,6 +95,8 @@ coresight-default-sink; coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading @@ -161,6 +164,9 @@ coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <4>; qcom,funnel-save-restore; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading arch/arm/boot/dts/qcom/msm8994-coresight.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,7 @@ interrupt-names = "byte-cntr-irq"; qcom,memory-size = <0x1400000>; qcom,tmc-flush-powerdown; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -89,6 +90,8 @@ coresight-default-sink; coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading @@ -157,6 +160,8 @@ coresight-child-list = <&funnel_in1>; coresight-child-ports = <6>; qcom,funnel-save-restore; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading
arch/arm/boot/dts/qcom/msm8916-coresight.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,7 @@ interrupt-names = "byte-cntr-irq"; qcom,memory-size = <0x100000>; qcom,tmc-flush-powerdown; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -92,6 +93,9 @@ coresight-child-ports = <0>; coresight-default-sink; coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading @@ -124,6 +128,9 @@ coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <4>; qcom,funnel-save-restore; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading
arch/arm/boot/dts/qcom/msm8939-coresight.dtsi +6 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ qcom,memory-size = <0x100000>; qcom,sg-enable; qcom,tmc-flush-powerdown; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -94,6 +95,8 @@ coresight-default-sink; coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading @@ -161,6 +164,9 @@ coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <4>; qcom,funnel-save-restore; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading
arch/arm/boot/dts/qcom/msm8994-coresight.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,7 @@ interrupt-names = "byte-cntr-irq"; qcom,memory-size = <0x1400000>; qcom,tmc-flush-powerdown; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -89,6 +90,8 @@ coresight-default-sink; coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading @@ -157,6 +160,8 @@ coresight-child-list = <&funnel_in1>; coresight-child-ports = <6>; qcom,funnel-save-restore; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading