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Commit ff1ce057 authored by Shawn Guo's avatar Shawn Guo Committed by Mark Brown
Browse files

regulator: anatop: improve precision of delay time 



For cpufreq example, it takes 13 steps (25 mV for one step) to increase
vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at
24 MHz for one step is ~2.67 uS, so the total delay time would be
~34.71 uS.  But the current calculation in the driver gives 39 uS.
Change the formula to have the addition of 1 be the last step, so that
we can get a more precise delay time.  For example above, the new
formula will give 35 uS.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 9ee417c0

drivers/regulator/anatop-regulator.c

+2 −2
Original line number Diff line number Diff line
@@ -80,8 +80,8 @@ static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg, 
		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);

		val = (val >> anatop_reg->delay_bit_shift) &

			((1 << anatop_reg->delay_bit_width) - 1);

		ret = (new_sel - old_sel) * ((LDO_RAMP_UP_UNIT_IN_CYCLES <<

			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1);

		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<

			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;

	}



	return ret;