Loading arch/arm/boot/dts/qcom/mpq8092-cdp.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -213,6 +213,13 @@ }; gpio@ce00 { /* GPIO 15 */ qcom,mode = <1>; /* Digital output */ qcom,output-type = <0>; /* CMOS logic */ qcom,pull = <5>; /* No pull */ qcom,vin-sel = <2>; /* VIN 2 */ qcom,src-sel = <2>; /* Function 1 */ qcom,out-strength = <2>; /* Medium */ qcom,master-en = <1>; /* Enable GPIO */ }; gpio@cf00 { /* GPIO 16 */ Loading arch/arm/boot/dts/qcom/mpq8092.dtsi +21 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,7 @@ serial1 = &blsp2_uart0; serial2 = &blsp2_uart3; spi12 = &spi_12; geni_ir1 = &geni_ir_1; }; memory { Loading Loading @@ -1497,6 +1498,26 @@ rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; qcom,msm-spss@fc5c3000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "qcom,msm-spss"; reg-names = "base"; reg = <0xfc5c3000 0x1000>; geni_ir_1: qcom,msm-geni-ir@fc5c1000 { compatible = "qcom,msm-geni-ir"; reg-names = "base"; reg = <0xfc5c1000 0x1000>; interrupts = <0 284 0>, <0 285 0>; interrupt-names = "geni-ir-core-irq", "geni-ir-wakeup-irq"; qcom,geni-ir-gpio-tx = <&msmgpio 8 0>; qcom,geni-ir-gpio-rx = <&msmgpio 9 0>; }; }; qcom,venus@fdce0000 { compatible = "qcom,pil-tz-generic"; reg = <0xfdce0000 0x4000>; Loading Loading
arch/arm/boot/dts/qcom/mpq8092-cdp.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -213,6 +213,13 @@ }; gpio@ce00 { /* GPIO 15 */ qcom,mode = <1>; /* Digital output */ qcom,output-type = <0>; /* CMOS logic */ qcom,pull = <5>; /* No pull */ qcom,vin-sel = <2>; /* VIN 2 */ qcom,src-sel = <2>; /* Function 1 */ qcom,out-strength = <2>; /* Medium */ qcom,master-en = <1>; /* Enable GPIO */ }; gpio@cf00 { /* GPIO 16 */ Loading
arch/arm/boot/dts/qcom/mpq8092.dtsi +21 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,7 @@ serial1 = &blsp2_uart0; serial2 = &blsp2_uart3; spi12 = &spi_12; geni_ir1 = &geni_ir_1; }; memory { Loading Loading @@ -1497,6 +1498,26 @@ rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; qcom,msm-spss@fc5c3000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "qcom,msm-spss"; reg-names = "base"; reg = <0xfc5c3000 0x1000>; geni_ir_1: qcom,msm-geni-ir@fc5c1000 { compatible = "qcom,msm-geni-ir"; reg-names = "base"; reg = <0xfc5c1000 0x1000>; interrupts = <0 284 0>, <0 285 0>; interrupt-names = "geni-ir-core-irq", "geni-ir-wakeup-irq"; qcom,geni-ir-gpio-tx = <&msmgpio 8 0>; qcom,geni-ir-gpio-rx = <&msmgpio 9 0>; }; }; qcom,venus@fdce0000 { compatible = "qcom,pil-tz-generic"; reg = <0xfdce0000 0x4000>; Loading