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Commit fe0cbb22 authored by Susheel Khiani's avatar Susheel Khiani
Browse files

ARM: dts: msm: Add SMR register mask bits for context banks for msmferrum 



Mask bits are programmed in SMR register's mask bits
field and are used for masking stream id bits which
are irrelevant for SID2CB matching process in SMR
table.

Change-Id: Ied3ab0450210cd419e23604a958103ddc15e87b7
Signed-off-by: default avatarSusheel Khiani <skhiani@codeaurora.org>
parent 3aed68ed

arch/arm/boot/dts/qcom/msm8909-iommu.dtsi

+27 −13
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
		reg = <0x1e22000 0x1000>;

		interrupts = <0 103 0>, <0 103 0>;

		qcom,iommu-ctx-sids = <0x1c0 0x1ca 0x1004>;

		qcom,iommu-sid-mask = <0x1 0x1 0x2>;

		label = "MSA0_Audio";

	};
@@ -44,7 +45,9 @@ 
	venus_ns: qcom,iommu-ctx@1e25000 {

		interrupts = <0 106 0>;

		qcom,iommu-ctx-sids = <0x800 0x807 0x808

					0x811 0x831>;

					0x811>;

		qcom,iommu-sid-mask = <0x0 0x0 0x27

					0x220>;

	};



	cpp: qcom,iommu-ctx@1e26000 {
@@ -76,10 +79,9 @@ 
		qcom,secure-context;

		reg = <0x1e31000 0x1000>;

		interrupts = <0 120 0>, <0 120 0>;

		qcom,iommu-ctx-sids = <0x1c01 0x1c02 0x1c03

					0x1c04 0x1c06 0x1c07

					0x1c08 0x1c09 0x1c0a

					0x1c0b 0x1c0c 0x1c0d >;

		qcom,iommu-ctx-sids = <0x1c01 0x1c02 0x1c03 0x1c04

					0x1c06 0x1c07 0x1c08 0x1c09

					0x1c0a 0x1c0b 0x1c0c 0x1c0d>;

		label = "wlan";

	};
@@ -90,8 +92,10 @@ 


	venus_sec_pixel: qcom,iommu-ctx@1e33000 {

		interrupts = <0 122 0>, <0 122 0>;

		qcom,iommu-ctx-sids = <0x900 0x909 0x90a

					0x90b 0x90e>;

		qcom,iommu-ctx-sids = <0x900 0x909 0x90a 0x90b

					0x90e>;

		qcom,iommu-sid-mask = <0x0 0x20 0x0 0x20

					0x0>;

	};



	venus_sec_bitstream: qcom,iommu-ctx@1e34000 {
@@ -112,17 +116,22 @@ 


	periph_rpm: qcom,iommu-ctx@1e37000 {

		interrupts = <0 228 0>, <0 228 0>;

		qcom,iommu-ctx-sids = <0x40>;

		qcom,iommu-sid-mask = <0x3f>;

	};



	periph_CE: qcom,iommu-ctx@1e38000 {

		interrupts = <0 229 0>;

		qcom,iommu-ctx-sids = <0xC4 0xC8 0xCC 0xD4 0xD7 0xD8

					0xDB 0xDC 0xDF 0xF4 0xF7 0xF8

					0xFB 0xFC 0xFF>;

		qcom,iommu-ctx-sids = <0xC4 0xC8 0xD4 0xD8

					0xF4 0xF8>;

		qcom,iommu-sid-mask = <0x23 0x27 0x3 0x7

					0x3 0x7>;

	};



	periph_BLSP: qcom,iommu-ctx@1e39000 {

		interrupts = <0 230 0>;

		qcom,iommu-ctx-sids = <0x280 0x288 0x28C 0x290>;

		qcom,iommu-sid-mask = <0x7 0x3 0x3 0x7>;

	};



	periph_SDC1: qcom,iommu-ctx@1e3a000 {
@@ -134,8 +143,10 @@ 
	};



	periph_audio: qcom,iommu-ctx@1e3c000 {

		qcom,iommu-ctx-sids = <0x1c2 0x1c4 0x1c6 0x1c8

					0x1cc 0x1ce 0x1cf>;

		qcom,iommu-ctx-sids = <0x1c2 0x1c4 0x1c8

					0x1cc 0x1cf>;

		qcom,iommu-sid-mask = <0x1 0x3 0x0

					0x3 0x0>;

		interrupts = <0 233 0>;

	};
@@ -148,7 +159,10 @@ 
		qcom,secure-context;

		reg = <0x1e3f000 0x1000>;

		interrupts = <0 152 0>;

		qcom,iommu-ctx-sids = <0xC0 0xD0 0xD3 0xF0 0xF3>;

		qcom,iommu-ctx-sids = <0xc0 0xd0 0xd3 0xf0

					0xf3>;

		qcom,iommu-sid-mask = <0x23 0x0 0x0 0x0

					0x0>;

		label = "periph_CE_secure";

	};

};