Loading arch/arm/boot/dts/msm8226-qrd.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -238,7 +238,7 @@ qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; qcom,clk-rates = <400000 25000000 50000000>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; Loading drivers/mmc/core/sd.c +14 −4 Original line number Diff line number Diff line Loading @@ -26,6 +26,12 @@ #include "sd.h" #include "sd_ops.h" #define UHS_SDR104_MIN_DTR (100 * 1000 * 1000) #define UHS_DDR50_MIN_DTR (50 * 1000 * 1000) #define UHS_SDR50_MIN_DTR (50 * 1000 * 1000) #define UHS_SDR25_MIN_DTR (25 * 1000 * 1000) #define UHS_SDR12_MIN_DTR (12.5 * 1000 * 1000) static const unsigned int tran_exp[] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 Loading Loading @@ -451,18 +457,22 @@ static void sd_update_bus_speed_mode(struct mmc_card *card) } if ((card->host->caps & MMC_CAP_UHS_SDR104) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104)) { (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104) && (card->host->f_max > UHS_SDR104_MIN_DTR)) { card->sd_bus_speed = UHS_SDR104_BUS_SPEED; } else if ((card->host->caps & MMC_CAP_UHS_DDR50) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50)) { (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50) && (card->host->f_max > UHS_DDR50_MIN_DTR)) { card->sd_bus_speed = UHS_DDR50_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50)) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR50)) { SD_MODE_UHS_SDR50) && (card->host->f_max > UHS_SDR50_MIN_DTR)) { card->sd_bus_speed = UHS_SDR50_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25)) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25)) { (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25) && (card->host->f_max > UHS_SDR25_MIN_DTR)) { card->sd_bus_speed = UHS_SDR25_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25 | Loading Loading
arch/arm/boot/dts/msm8226-qrd.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -238,7 +238,7 @@ qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; qcom,clk-rates = <400000 25000000 50000000>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; Loading
drivers/mmc/core/sd.c +14 −4 Original line number Diff line number Diff line Loading @@ -26,6 +26,12 @@ #include "sd.h" #include "sd_ops.h" #define UHS_SDR104_MIN_DTR (100 * 1000 * 1000) #define UHS_DDR50_MIN_DTR (50 * 1000 * 1000) #define UHS_SDR50_MIN_DTR (50 * 1000 * 1000) #define UHS_SDR25_MIN_DTR (25 * 1000 * 1000) #define UHS_SDR12_MIN_DTR (12.5 * 1000 * 1000) static const unsigned int tran_exp[] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 Loading Loading @@ -451,18 +457,22 @@ static void sd_update_bus_speed_mode(struct mmc_card *card) } if ((card->host->caps & MMC_CAP_UHS_SDR104) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104)) { (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104) && (card->host->f_max > UHS_SDR104_MIN_DTR)) { card->sd_bus_speed = UHS_SDR104_BUS_SPEED; } else if ((card->host->caps & MMC_CAP_UHS_DDR50) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50)) { (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50) && (card->host->f_max > UHS_DDR50_MIN_DTR)) { card->sd_bus_speed = UHS_DDR50_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50)) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR50)) { SD_MODE_UHS_SDR50) && (card->host->f_max > UHS_SDR50_MIN_DTR)) { card->sd_bus_speed = UHS_SDR50_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25)) && (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25)) { (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25) && (card->host->f_max > UHS_SDR25_MIN_DTR)) { card->sd_bus_speed = UHS_SDR25_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25 | Loading