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Commit fc163c4c authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: Rename readll/writell to readq/writeq"

parents a80d496d 09b046fe

arch/arm/include/asm/io.h

+16 −16
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ static inline void __raw_writel_no_log(u32 val, volatile void __iomem *addr) 
		     : "r" (val));

}



static inline void __raw_writell_no_log(u64 val, volatile void __iomem *addr)

static inline void __raw_writeq_no_log(u64 val, volatile void __iomem *addr)

{

	register u64 v asm ("r2");
@@ -122,7 +122,7 @@ static inline u32 __raw_readl_no_log(const volatile void __iomem *addr) 
	return val;

}



static inline u64 __raw_readll_no_log(const volatile void __iomem *addr)

static inline u64 __raw_readq_no_log(const volatile void __iomem *addr)

{

	register u64 val asm ("r2");
@@ -152,7 +152,7 @@ static inline u64 __raw_readll_no_log(const volatile void __iomem *addr) 
#define __raw_writeb(v, a)	__raw_write_logged((v), (a), b)

#define __raw_writew(v, a)	__raw_write_logged((v), (a), w)

#define __raw_writel(v, a)	__raw_write_logged((v), (a), l)

#define __raw_writell(v, a)	__raw_write_logged((v), (a), ll)

#define __raw_writeq(v, a)	__raw_write_logged((v), (a), q)



#define __raw_read_logged(a, _l, _t)		({ \

	unsigned _t __a; \
@@ -170,7 +170,7 @@ static inline u64 __raw_readll_no_log(const volatile void __iomem *addr) 
#define __raw_readb(a)		__raw_read_logged((a), b, char)

#define __raw_readw(a)		__raw_read_logged((a), w, short)

#define __raw_readl(a)		__raw_read_logged((a), l, int)

#define __raw_readll(a)		__raw_read_logged((a), ll, long long)

#define __raw_readq(a)		__raw_read_logged((a), q, long long)



/*

 * Architecture ioremap implementation.
@@ -353,30 +353,30 @@ extern void _memset_io(volatile void __iomem *, int, size_t); 
					__raw_readw(c)); __r; })

#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \

					__raw_readl(c)); __r; })

#define readll_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \

					__raw_readll(c)); __r; })

#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \

					__raw_readq(c)); __r; })

#define readl_relaxed_no_log(c) ({ u32 __r = le32_to_cpu((__force __le32) \

					__raw_readl_no_log(c)); __r; })

#define readll_relaxed_no_log(c) ({ u64 __r = le64_to_cpu((__force __le64) \

					__raw_readll_no_log(c)); __r; })

#define readq_relaxed_no_log(c) ({ u64 __r = le64_to_cpu((__force __le64) \

					__raw_readq_no_log(c)); __r; })





#define writeb_relaxed(v,c)	__raw_writeb(v,c)

#define writew_relaxed(v,c)	__raw_writew((__force u16) cpu_to_le16(v),c)

#define writel_relaxed(v,c)	__raw_writel((__force u32) cpu_to_le32(v),c)

#define writell_relaxed(v,c)	__raw_writell((__force u64) cpu_to_le64(v),c)

#define writeq_relaxed(v,c)	__raw_writeq((__force u64) cpu_to_le64(v),c)

#define writel_relaxed_no_log(v, c) __raw_writel_no_log((__force u32) cpu_to_le32(v),c)

#define writell_relaxed_no_log(v, c) __raw_writell_no_log((__force u64) cpu_to_le64(v),c)

#define writeq_relaxed_no_log(v, c) __raw_writeq_no_log((__force u64) cpu_to_le64(v),c)



#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })

#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })

#define readll(c)		({ u64 __v = readll_relaxed(c); __iormb(); __v; })

#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(); __v; })



#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })

#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })

#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })

#define writell(v, c)		({ __iowmb(); writell_relaxed(v, c); })

#define writeq(v, c)		({ __iowmb(); writeq_relaxed(v, c); })



#define readsb(p,d,l)		__raw_readsb(p,d,l)

#define readsw(p,d,l)		__raw_readsw(p,d,l)
@@ -412,20 +412,20 @@ extern void _memset_io(volatile void __iomem *, int, size_t); 
#define ioread8(p)	({ unsigned int __v = __raw_readb(p); __iormb(); __v; })

#define ioread16(p)	({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })

#define ioread32(p)	({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })

#define ioread64(p)	({ unsigned int __v = le64_to_cpu((__force __le64)__raw_readll(p)); __iormb(); __v; })

#define ioread64(p)	({ unsigned int __v = le64_to_cpu((__force __le64)__raw_readq(p)); __iormb(); __v; })



#define ioread16be(p)	({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })

#define ioread32be(p)	({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })

#define ioread64be(p)	({ unsigned int __v = be64_to_cpu((__force __be64)__raw_readll(p)); __iormb(); __v; })

#define ioread64be(p)	({ unsigned int __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(); __v; })



#define iowrite8(v,p)	({ __iowmb(); __raw_writeb(v, p); })

#define iowrite16(v,p)	({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })

#define iowrite32(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })

#define iowrite64(v,p)	({ __iowmb(); __raw_writell((__force __u64)cpu_to_le64(v), p); })

#define iowrite64(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_le64(v), p); })



#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })

#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })

#define iowrite64be(v,p) ({ __iowmb(); __raw_writell((__force __u64)cpu_to_be64(v), p); })

#define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })



#define ioread8_rep(p,d,c)	__raw_readsb(p,d,c)

#define ioread16_rep(p,d,c)	__raw_readsw(p,d,c)

arch/arm/mach-msm/cpr-regulator.c

+1 −1
Original line number Diff line number Diff line
@@ -252,7 +252,7 @@ static u64 cpr_read_efuse_row(struct cpr_regulator *cpr_vreg, u32 row_num) 
	} rsp;



	if (cpr_vreg->use_tz_api != true) {

		efuse_bits = readll_relaxed(cpr_vreg->efuse_base

		efuse_bits = readq_relaxed(cpr_vreg->efuse_base

			+ row_num * BYTES_PER_FUSE_ROW);

		return efuse_bits;

	}

arch/arm/mach-msm/include/mach/iommu_hw-v1.h

+27 −27
Original line number Diff line number Diff line
@@ -17,21 +17,21 @@ 
#define CTX_OFFSET 0x8000



#define GET_GLOBAL_REG(reg, base) (readl_relaxed((base) + (reg)))

#define GET_GLOBAL_REG_L(reg, base) (readll_relaxed((base) + (reg)))

#define GET_GLOBAL_REG_Q(reg, base) (readq_relaxed((base) + (reg)))

#define GET_CTX_REG(reg, base, ctx) \

	(readl_relaxed((base) + CTX_OFFSET + (reg) + ((ctx) << CTX_SHIFT)))

#define GET_CTX_REG_L(reg, base, ctx) \

	(readll_relaxed((base) + CTX_OFFSET + (reg) + ((ctx) << CTX_SHIFT)))

#define GET_CTX_REG_Q(reg, base, ctx) \

	(readq_relaxed((base) + CTX_OFFSET + (reg) + ((ctx) << CTX_SHIFT)))



#define SET_GLOBAL_REG(reg, base, val)	writel_relaxed((val), ((base) + (reg)))

#define SET_GLOBAL_REG_L(reg, base, val) \

	(writell_relaxed((val), ((base) + (reg))))

#define SET_GLOBAL_REG_Q(reg, base, val) \

	(writeq_relaxed((val), ((base) + (reg))))



#define SET_CTX_REG(reg, base, ctx, val) \

	writel_relaxed((val), \

		((base) + CTX_OFFSET + (reg) + ((ctx) << CTX_SHIFT)))

#define SET_CTX_REG_L(reg, base, ctx, val) \

	writell_relaxed((val), \

#define SET_CTX_REG_Q(reg, base, ctx, val) \

	writeq_relaxed((val), \

		((base) + CTX_OFFSET + (reg) + ((ctx) << CTX_SHIFT)))



/* Wrappers for numbered registers */
@@ -44,8 +44,8 @@ 
#define GET_CONTEXT_FIELD(b, c, r, F) \

	GET_FIELD(((b) + CTX_OFFSET + (r) + ((c) << CTX_SHIFT)), \

			r##_##F##_MASK, r##_##F##_SHIFT)

#define GET_CONTEXT_FIELD_L(b, c, r, F) \

	GET_FIELD_L(((b) + CTX_OFFSET + (r) + ((c) << CTX_SHIFT)), \

#define GET_CONTEXT_FIELD_Q(b, c, r, F) \

	GET_FIELD_Q(((b) + CTX_OFFSET + (r) + ((c) << CTX_SHIFT)), \

			r##_##F##_MASK, r##_##F##_SHIFT)



#define SET_GLOBAL_FIELD(b, r, F, v) \
@@ -53,8 +53,8 @@ 
#define SET_CONTEXT_FIELD(b, c, r, F, v) \

	SET_FIELD(((b) + CTX_OFFSET + (r) + ((c) << CTX_SHIFT)), \

			r##_##F##_MASK, r##_##F##_SHIFT, (v))

#define SET_CONTEXT_FIELD_L(b, c, r, F, v) \

	SET_FIELD_L(((b) + CTX_OFFSET + (r) + ((c) << CTX_SHIFT)), \

#define SET_CONTEXT_FIELD_Q(b, c, r, F, v) \

	SET_FIELD_Q(((b) + CTX_OFFSET + (r) + ((c) << CTX_SHIFT)), \

			r##_##F##_MASK, r##_##F##_SHIFT, (v))



/* Wrappers for numbered field registers */
@@ -64,8 +64,8 @@ 
	GET_FIELD(((b) + ((n) << 2) + (r)), r##_##F##_MASK, r##_##F##_SHIFT)



#define GET_FIELD(addr, mask, shift) ((readl_relaxed(addr) >> (shift)) & (mask))

#define GET_FIELD_L(addr, mask, shift) \

	((readll_relaxed(addr) >> (shift)) & (mask))

#define GET_FIELD_Q(addr, mask, shift) \

	((readq_relaxed(addr) >> (shift)) & (mask))



#define SET_FIELD(addr, mask, shift, v) \

do { \
@@ -74,10 +74,10 @@ do { \ 
			(mask)) << (shift)), addr); \

} while (0)



#define SET_FIELD_L(addr, mask, shift, v) \

#define SET_FIELD_Q(addr, mask, shift, v) \

do { \

	u64 t = readll_relaxed(addr); \

	writell_relaxed((t & ~(((u64) mask) << (shift))) + (((v) & \

	u64 t = readq_relaxed(addr); \

	writeq_relaxed((t & ~(((u64) mask) << (shift))) + (((v) & \

			((u64) mask)) << (shift)), addr); \

} while (0)
@@ -91,7 +91,7 @@ do { \ 
#define SET_IDR1(b, N, v)        SET_GLOBAL_REG(IDR1, (b), (v))

#define SET_IDR2(b, N, v)        SET_GLOBAL_REG(IDR2, (b), (v))

#define SET_IDR7(b, N, v)        SET_GLOBAL_REG(IDR7, (b), (v))

#define SET_GFAR(b, v)           SET_GLOBAL_REG_L(GFAR, (b), (v))

#define SET_GFAR(b, v)           SET_GLOBAL_REG_Q(GFAR, (b), (v))

#define SET_GFSR(b, v)           SET_GLOBAL_REG(GFSR, (b), (v))

#define SET_GFSRRESTORE(b, v)    SET_GLOBAL_REG(GFSRRESTORE, (b), (v))

#define SET_GFSYNR0(b, v)        SET_GLOBAL_REG(GFSYNR0, (b), (v))
@@ -130,7 +130,7 @@ do { \ 
#define GET_IDR1(b, N)           GET_GLOBAL_REG(IDR1, (b))

#define GET_IDR2(b, N)           GET_GLOBAL_REG(IDR2, (b))

#define GET_IDR7(b, N)           GET_GLOBAL_REG(IDR7, (b))

#define GET_GFAR(b)              GET_GLOBAL_REG_L(GFAR, (b))

#define GET_GFAR(b)              GET_GLOBAL_REG_Q(GFAR, (b))

#define GET_GFSR(b)              GET_GLOBAL_REG(GFSR, (b))

#define GET_GFSRRESTORE(b)       GET_GLOBAL_REG(GFSRRESTORE, (b))

#define GET_GFSYNR0(b)           GET_GLOBAL_REG(GFSYNR0, (b))
@@ -219,10 +219,10 @@ do { \ 
#define GET_CONTEXTIDR(b, c)     GET_CTX_REG(CB_CONTEXTIDR, (b), (c))

#define GET_PRRR(b, c)           GET_CTX_REG(CB_PRRR, (b), (c))

#define GET_NMRR(b, c)           GET_CTX_REG(CB_NMRR, (b), (c))

#define GET_PAR(b, c)            GET_CTX_REG_L(CB_PAR, (b), (c))

#define GET_PAR(b, c)            GET_CTX_REG_Q(CB_PAR, (b), (c))

#define GET_FSR(b, c)            GET_CTX_REG(CB_FSR, (b), (c))

#define GET_FSRRESTORE(b, c)     GET_CTX_REG(CB_FSRRESTORE, (b), (c))

#define GET_FAR(b, c)            GET_CTX_REG_L(CB_FAR, (b), (c))

#define GET_FAR(b, c)            GET_CTX_REG_Q(CB_FAR, (b), (c))

#define GET_FSYNR0(b, c)         GET_CTX_REG(CB_FSYNR0, (b), (c))

#define GET_FSYNR1(b, c)         GET_CTX_REG(CB_FSYNR1, (b), (c))

#define GET_TLBIVA(b, c)         GET_CTX_REG(CB_TLBIVA, (b), (c))
@@ -919,15 +919,15 @@ do { \ 
/* LPAE format */



/* Translation Table Base Register 0: CB_TTBR */

#define SET_TTBR0(b, c, v)       SET_CTX_REG_L(CB_TTBR0, (b), (c), (v))

#define SET_TTBR1(b, c, v)       SET_CTX_REG_L(CB_TTBR1, (b), (c), (v))

#define SET_TTBR0(b, c, v)       SET_CTX_REG_Q(CB_TTBR0, (b), (c), (v))

#define SET_TTBR1(b, c, v)       SET_CTX_REG_Q(CB_TTBR1, (b), (c), (v))



#define SET_CB_TTBR0_ASID(b, c, v)  SET_CONTEXT_FIELD_L(b, c, CB_TTBR0, ASID, v)

#define SET_CB_TTBR0_ADDR(b, c, v)  SET_CONTEXT_FIELD_L(b, c, CB_TTBR0, ADDR, v)

#define SET_CB_TTBR0_ASID(b, c, v)  SET_CONTEXT_FIELD_Q(b, c, CB_TTBR0, ASID, v)

#define SET_CB_TTBR0_ADDR(b, c, v)  SET_CONTEXT_FIELD_Q(b, c, CB_TTBR0, ADDR, v)



#define GET_CB_TTBR0_ASID(b, c)     GET_CONTEXT_FIELD_L(b, c, CB_TTBR0, ASID)

#define GET_CB_TTBR0_ADDR(b, c)     GET_CONTEXT_FIELD_L(b, c, CB_TTBR0, ADDR)

#define GET_CB_TTBR0(b, c)          GET_CTX_REG_L(CB_TTBR0, (b), (c))

#define GET_CB_TTBR0_ASID(b, c)     GET_CONTEXT_FIELD_Q(b, c, CB_TTBR0, ASID)

#define GET_CB_TTBR0_ADDR(b, c)     GET_CONTEXT_FIELD_Q(b, c, CB_TTBR0, ADDR)

#define GET_CB_TTBR0(b, c)          GET_CTX_REG_Q(CB_TTBR0, (b), (c))



/* Translation Table Base Control Register: CB_TTBCR */

#define SET_CB_TTBCR_T0SZ(b, c, v)   SET_CONTEXT_FIELD(b, c, CB_TTBCR, T0SZ, v)

arch/arm/mach-msm/rpm_master_stat.c

+4 −4
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static int msm_rpm_master_copy_stats( 
		SNPRINTF(buf, count, "%s\n",

				GET_MASTER_NAME(master_cnt, prvdata));



		record.shutdown_req = readll_relaxed(prvdata->reg_base +

		record.shutdown_req = readq_relaxed(prvdata->reg_base +

			(master_cnt * pdata->master_offset +

			offsetof(struct msm_rpm_master_stats, shutdown_req)));
@@ -119,7 +119,7 @@ static int msm_rpm_master_copy_stats( 
			GET_FIELD(record.shutdown_req),

			record.shutdown_req);



		record.wakeup_ind = readll_relaxed(prvdata->reg_base +

		record.wakeup_ind = readq_relaxed(prvdata->reg_base +

			(master_cnt * pdata->master_offset +

			offsetof(struct msm_rpm_master_stats, wakeup_ind)));
@@ -127,7 +127,7 @@ static int msm_rpm_master_copy_stats( 
			GET_FIELD(record.wakeup_ind),

			record.wakeup_ind);



		record.bringup_req = readll_relaxed(prvdata->reg_base +

		record.bringup_req = readq_relaxed(prvdata->reg_base +

			(master_cnt * pdata->master_offset +

			offsetof(struct msm_rpm_master_stats, bringup_req)));
@@ -135,7 +135,7 @@ static int msm_rpm_master_copy_stats( 
			GET_FIELD(record.bringup_req),

			record.bringup_req);



		record.bringup_ack = readll_relaxed(prvdata->reg_base +

		record.bringup_ack = readq_relaxed(prvdata->reg_base +

			(master_cnt * pdata->master_offset +

			offsetof(struct msm_rpm_master_stats, bringup_ack)));

drivers/gpu/msm/kgsl_iommu.c

+2 −2
Original line number Diff line number Diff line
@@ -1697,7 +1697,7 @@ static int kgsl_iommu_start(struct kgsl_mmu *mmu) 
			}

			if (sizeof(phys_addr_t) > sizeof(unsigned long)) {

				iommu_unit->dev[j].default_ttbr0 =

						KGSL_IOMMU_GET_CTX_REG_LL(iommu,

						KGSL_IOMMU_GET_CTX_REG_Q(iommu,

						iommu_unit,

						iommu_unit->dev[j].ctx_id,

						TTBR0);
@@ -1969,7 +1969,7 @@ static int kgsl_iommu_default_setstate(struct kgsl_mmu *mmu, 
			pt_val &= ~KGSL_IOMMU_CTX_TTBR0_ADDR_MASK;

			pt_val |= pt_base;

			if (sizeof(phys_addr_t) > sizeof(unsigned long)) {

				KGSL_IOMMU_SET_CTX_REG_LL(iommu,

				KGSL_IOMMU_SET_CTX_REG_Q(iommu,

					(&iommu->iommu_units[i]),

					KGSL_IOMMU_CONTEXT_USER, TTBR0, pt_val);

			} else {