Loading arch/arm/mach-msm/cache_erp.c +0 −2 Original line number Diff line number Diff line Loading @@ -23,7 +23,6 @@ #include <mach/msm_iomap.h> #include <mach/socinfo.h> #include <asm/cputype.h> #include "acpuclock.h" #define CESR_DCTPE BIT(0) #define CESR_DCDPE BIT(1) Loading Loading @@ -293,7 +292,6 @@ static irqreturn_t msm_l1_erp_irq(int irq, void *dev_id) if (print_regs) { pr_alert("L1 / TLB Error detected on CPU %d!\n", cpu); pr_alert("\tCESR = 0x%08x\n", cesr); pr_alert("\tCPU speed = %lu\n", acpuclk_get_rate(cpu)); pr_alert("\tMIDR = 0x%08x\n", read_cpuid_id()); msm_erp_dump_regions(); } Loading Loading
arch/arm/mach-msm/cache_erp.c +0 −2 Original line number Diff line number Diff line Loading @@ -23,7 +23,6 @@ #include <mach/msm_iomap.h> #include <mach/socinfo.h> #include <asm/cputype.h> #include "acpuclock.h" #define CESR_DCTPE BIT(0) #define CESR_DCDPE BIT(1) Loading Loading @@ -293,7 +292,6 @@ static irqreturn_t msm_l1_erp_irq(int irq, void *dev_id) if (print_regs) { pr_alert("L1 / TLB Error detected on CPU %d!\n", cpu); pr_alert("\tCESR = 0x%08x\n", cesr); pr_alert("\tCPU speed = %lu\n", acpuclk_get_rate(cpu)); pr_alert("\tMIDR = 0x%08x\n", read_cpuid_id()); msm_erp_dump_regions(); } Loading