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Commit fbf22957 authored by Shubhraprakash Das's avatar Shubhraprakash Das
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msm: kgsl: Protect additional registers for A430 and A420 



Protect additional range of registers which should not be
accessed by GPU. This also prevents xpu violation for
addresses that are protected via xpu and the GPU's protection
scheme.

CRs-Fixed: 771296
Change-Id: I17463f6240d1d44ffab73ddd0e737652b33c3589
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent e4d39e9e

drivers/gpu/msm/adreno_a4xx.c

+21 −0
Original line number Diff line number Diff line
@@ -649,6 +649,27 @@ static void a4xx_protect_init(struct adreno_device *adreno_dev) 
	/* VPC registers */

	adreno_set_protected_registers(adreno_dev, &index, 0xE60, 1);



	if (adreno_is_a430(adreno_dev)) {

		/*

		 * Protect additional registers that should not be

		 * accessed by GPU

		 */

		adreno_set_protected_registers(adreno_dev, &index, 0x2c00, 10);

		adreno_set_protected_registers(adreno_dev, &index, 0x3000, 7);

		adreno_set_protected_registers(adreno_dev, &index, 0x3080, 6);

		adreno_set_protected_registers(adreno_dev, &index, 0x3140, 11);

		adreno_set_protected_registers(adreno_dev, &index, 0x3940, 10);

		adreno_set_protected_registers(adreno_dev, &index, 0x3D40, 9);

		adreno_set_protected_registers(adreno_dev, &index, 0x3F40, 7);

		adreno_set_protected_registers(adreno_dev, &index, 0x3FC0, 6);

	} else if (adreno_is_a420(adreno_dev)) {

		/*

		 * Protect XPU range and range of registers that may fall

		 * under XPU protection

		 */

		adreno_set_protected_registers(adreno_dev, &index, 0x3300, 8);

	}



	/* SMMU registers */

	iommu_regs = kgsl_mmu_get_prot_regs(&device->mmu);

	if (iommu_regs)